Ultra-low jitter low-power W/D-band phase-locked loop using power-gating injection-locked frequency multiplierbased phase detector

An operating method of a phase-locked loop comprising a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD), the operating method comprising:

• outputting, by a replica voltage controlled oscillator (R-VCO) of the PG-ILFM PD, an output signal SILFM by repeatedly manipulating an input voltage of the R-VCO based on a reference signal SREF;
• and
• receiving, by a fundamental sampling phase detector (FSPD) of the PG-ILFM PD, the output signal SILFM of the R-VCO as a reference signal for sampling and detecting a phase error of a main voltage controlled oscillator (M-VCO), wherein outputting, by the R-VCO of the PG-ILFM PD, the output signal SILFM comprises using the R-VCO having a structure identical with a structure of the M-VCO to multiply a frequency of the reference signal SREF.