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US 11,894,857 B2Granted
Readout circuit, signal quantizing method and device, and computer device
AssigneeShanghai United Imaging Microelectronics Technology Co., Ltd.
InventorsRong Wu, Longheng Luo, Jieyou Zhao, Mingfeng Chen
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Abstract
Disclosed are a readout circuit, a signal quantizing method, a signal quantizing device, and a computer device. The readout circuit includes: a signal sampler, including a plurality of channels; a plurality of integrators, connected to the plurality of channels and having a one-to-one relationship with the plurality of channels; a signal processor, including a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively; and an analog-digital converter. An input of the analog-digital converter is connected to an output of the first operational amplifier.
Claims17
A readout circuit, comprising:
- a signal sampler, comprising a plurality of channels;
- a plurality of integrators, connected to the plurality of channels and having a one-to-one relationship with the plurality of channels;
- a signal processor, comprising a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively;
- and
- an analog-digital converter, an input of the analog-digital converter being connected to an output of the first operational amplifier;
- wherein the readout circuit further comprises a signal modelling channel;
- the signal modelling channel comprises a second operational amplifier;
- and
- an output of the second operational amplifier is an output of the signal modelling channel and is connected to the input of the analog-digital converter.
6 more elements
A readout circuit, comprising:
- a signal processing circuit, comprising a plurality of sampling capacitors and a signal processor, one terminal of each of the plurality of sampling capacitors being connected to an input of the signal processor, and at least one of the plurality of sampling capacitors being configured to sample at least one signal;
- a randomizing circuit, configured to randomize an order in which the plurality of sampling capacitors are flip-flopped to the signal processor;
- and
- an analog-digital converter, an input end of the analog-digital converter being connected to an output of the signal processor.
1 more element
A readout circuit, comprising:
- a main signal channel, configured to process an electric charge signal together with an interference noise signal to obtain a first processed electric charge signal, and the interference noise signal being noise information generated by the readout circuit;
- a signal modelling channel, configured to process the interference noise signal to obtain a second processed electric charge signal;
- an analog-digital converter, configured to perform a processing of restraining noise on the first processed electric charge signal and the second processed electric charge signal, to obtain a quantized result corresponding to the electric charge signal.
A readout circuit, comprising:
- a signal sampler, comprising a plurality of channels;
- a plurality of integrators, connected to the plurality of channels and having a one-to-one relationship with the plurality of channels;
- a signal processor, comprising a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively;
- and
- an analog-digital converter, an input of the analog-digital converter being connected to an output of the first operational amplifier;
- wherein the signal processor further comprises a resetting capacitor and holding switches;
- a first terminal of the resetting capacitor is connected to the sampling input of the first operational amplifier, and a second terminal of the resetting capacitor is connected to the output of the first operational amplifier;
- one of the holding switches is connected between the first terminal of the resetting capacitor and a common-mode voltage input of the signal processor, and another of the holding switches is connected between the second terminal of the resetting capacitor and a common-mode voltage output of the signal processor.
5 more elements
A readout circuit, comprising:
- a signal sampler, comprising a plurality of channels;
- a plurality of integrators, connected to the plurality of channels and having a one-to-one relationship with the plurality of channels;
- a signal processor, comprising a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively;
- and
- an analog-digital converter, an input of the analog-digital converter being connected to an output of the first operational amplifier;
- wherein the readout circuit further comprises a plurality of sampling capacitors, and at least one of the plurality of sampling capacitors is configured to be connected to the outputs of the plurality of integrators, respectively;
- and
- the readout circuit further comprises a randomizing circuit, and the randomizing circuit is configured to randomize an order in which the plurality of sampling capacitors are flip-flopped to the signal processor.
5 more elements
Dependencies are inferred from the claim text.