Differential signal skew calibration circuit and semiconductor memory
AssigneeChangxin Memory Technologies, Inc.
InventorPengzhou Su
Life of this patent
Estimating the term…
Abstract
Provided are a differential signal skew calibration circuit and a semiconductor memory. The differential signal skew calibration circuit may acquire a phase relationship of a differential signals through a phase detection circuit. A phase adjustment control circuit may generate a phase calibration control instruction according to the phase relationship of the differential signals to control a phase calibration circuit to calibrate a phase skew of the input differential signals.
Claims18
A differential signal skew calibration circuit, comprising:
- a phase calibration circuit, configured to calibrate a phase of differential signals;
- a phase detection circuit, a first end of the phase detection circuit being connected with an output end of the phase calibration circuit, wherein the phase detection circuit is configured to perform a preset logical operation on the differential signals to generate a phase difference pulse signal, and acquire a phase relationship of the differential signals according to the differential signals and the phase difference pulse signal;
- and
- a phase adjustment control circuit, a first end of the phase adjustment control circuit being connected with a second end of the phase detection circuit, a second end of the phase adjustment control circuit being connected with a control end of the phase calibration circuit, wherein the phase adjustment control circuit is configured to receive the phase relationship, generate a phase calibration control instruction according to the phase relationship, and send the phase calibration control instruction to the phase calibration circuit to implement skew calibration of the differential signals;
- wherein the phase detection circuit comprises:
- a first detection circuit, a first end of the first detection circuit being connected with the output end of the phase calibration circuit, wherein the first detection circuit is configured to perform the preset logical operation on the differential signals to generate a first phase difference pulse signal and a second phase difference pulse signal;
- and
- a second detection circuit, a first end of the second detection circuit being connected with a second end of the first detection circuit, a second end of the second detection circuit being connected with the first end of the phase adjustment control circuit, wherein the second detection circuit is configured to compare between amplitudes of the first phase difference pulse signal and the second phase difference pulse signal to obtain the phase relationship, and send the phase relationship to the phase adjustment control circuit.
A semiconductor memory, comprising a differential signal skew calibration circuit, wherein the differential signal skew calibration circuit comprises:
- a phase calibration circuit, configured to calibrate a phase of differential signals;
- a phase detection circuit, a first end of the phase detection circuit being connected with an output end of the phase calibration circuit, wherein the phase detection circuit is configured to perform a preset logical operation on the differential signals to generate a phase difference pulse signal, and acquire a phase relationship of the differential signals according to the differential signals and the phase difference pulse signal;
- and
- a phase adjustment control circuit, a first end of the phase adjustment control circuit being connected with a second end of the phase detection circuit, a second end of the phase adjustment control circuit being connected with a control end of the phase calibration circuit, wherein the phase adjustment control circuit is configured to receive the phase relationship, generate a phase calibration control instruction according to the phase relationship, and send the phase calibration control instruction to the phase calibration circuit to implement skew calibration of the differential signals;
- the phase detection circuit comprises:
- a first detection circuit, a first end of the first detection circuit being connected with the output end of the phase calibration circuit, wherein the first detection circuit is configured to perform the preset logical operation on the differential signals to generate a first phase difference pulse signal and a second phase difference pulse signal;
- and
- a second detection circuit, a first end of the second detection circuit being connected with a second end of the first detection circuit, a second end of the second detection circuit being connected with the first end of the phase adjustment control circuit, wherein the second detection circuit is configured to compare between amplitudes of the first phase difference pulse signal and the second phase difference pulse signal to obtain the phase relationship, and send the phase relationship to the phase adjustment control circuit.
Dependencies are inferred from the claim text.