Duty cycle distortion (DCD) sampling in a low-swing transmitter
AssigneeMellanox Technologies, Ltd.
InventorsIgal Kushnir, Naor Peretz, Roi Levi
Life of this patent
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Abstract
Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.
Claims19
A chip-to-chip (C2C) transmitter comprising:
- an output driver to receive an input signal and output an intermediate signal corresponding to the input signal on an output node, wherein the input signal comprises a first signal swing corresponding to a supply voltage of the output driver;
- an attenuator coupled to the output node of the output driver, the attenuator to receive the intermediate signal and output an output signal, wherein the output signal comprises a second signal swing that is less than the first signal swing;
- and
- a duty cycle correction (DCC) loop coupled to the output node of the output driver, the DCC loop to sample the intermediate signal at the output node of the output driver to estimate and correct for duty cycle distortion (DCD) at the output node, wherein the attenuator is a passive continuous-time linear equalization (CTLE) circuit.
A source synchronous chip-to-chip (C2C) transmitter comprising:
- a first signal source comprising a processing device, a data channel, and a first serializer, the first serializer, wherein the first serializer is to receive a clock signal from a clock tree coupled to a phased-locked loop (PLL);
- a first output driver comprising a first complementary metal-oxide semiconductor (CMOS) amplifier and a first attenuator coupled to an output of the first CMOS amplifier;
- and
- a first duty cycle correction (DCC) loop coupled to the first signal source and the first output driver, wherein the first DCC loop is to estimate and correct for first duty cycle distortion (DCD) at the output of the first CMOS amplifier.
A source synchronous chip-to-chip (C2C) transmitter comprising:
- a first signal source;
- a first output driver comprising a first complementary metal-oxide semiconductor (CMOS) amplifier and a first attenuator coupled to an output of the first CMOS amplifier;
- and
- a first duty cycle correction (DCC) loop coupled to the first signal source and the first output driver, wherein the first DCC loop is to estimate and correct for first duty cycle distortion (DCD) at the output of the first CMOS amplifier, wherein the first attenuator is a passive continuous-time linear equalization (CTLE) circuit.
A circuit comprising:
- a complementary metal-oxide semiconductor (CMOS) amplifier;
- an attenuator coupled to an output of the CMOS amplifier;
- and
- a duty cycle distortion (DCD) estimation block coupled to an output of the CMOS amplifier to measure DCD at the output of the CMOS amplifier, wherein the attenuator is a passive continuous-time linear equalization (CTLE) circuit.
Dependencies are inferred from the claim text.