Output buffer for a swappable single conductor interface

An output buffer for a swappable single conductor interface having a first pin and a second pin, wherein either of the first pin or second pins is couplable to an input/output line or to an external capacitor line, the output buffer including:

• (a) a first transistor having a conduction channel coupled between the first pin and a reference potential, and a gate;
• (b) a second transistor having a conduction channel coupled between the second pin and the reference potential, and a gate;
• (c) a third transistor having a conduction channel coupled between the first and second pins, and a gate;
• and
• (d) a driver control circuit coupled to the gates of the first, second, and third transistors and configured (1) to make the first transistor operable in response to a pin-connection flag signal having a first state indicating that the second pin is coupled to a storage capacitor, and in response to a first enable signal, (2) to make the second transistor operable in response to the pin-connection flag signal having a second state indicating that the first pin is coupled to a storage capacitor, and in response to the first enable signal, and (3) to make the third transistor operable in response to a second enable signal;
• wherein the operable third transistor and the operable one of the first and second transistors have complementary ON or OFF conductive states in response to command and data signals received by the driver control circuit;
• and
• wherein the coupled input/output line is connected to the coupled external capacitor line through the operable third transistor when the operable third transistor is set to the ON conductive state.

An output buffer for a swappable single conductor interface having a first pin and a second pin, the output buffer including:

• (a) at least one unit cell each including:
• (1) a first transistor having a conduction channel coupled between the first pin and a reference potential, and a gate;
• (2) a second transistor having a conduction channel coupled between the second pin and the reference potential, and a gate;
• (3) a third transistor having a conduction channel coupled between the first and second pins, and a gate;
• and
• (b) a driver control circuit coupled to the gates of the first, second, and third transistors in each unit cell and configured, for selected ones of the at least one unit cell, (1) to make the first transistor within the selected unit cells operable in response to a pin-connection flag signal having a first state indicating that the second pin is coupled to a storage capacitor, and in response to a first enable signal, (2) to make the second transistor within the selected unit cells operable in response to the pin-connection flag signal having a second state indicating that the first pin is coupled to a storage capacitor, and in response to the first enable signal, and (3) to make the third transistor within the selected unit cells operable in response to a second enable signal;
• wherein within the selected unit cells the operable third transistor and the operable one of the first and second transistors have complementary states in response to command and data signals received by the driver control circuit;
• and
• wherein within the selected unit cells the operable third transistor is selectively settable to a conductive state to convey charge through a conductive path from an input/output line coupled to one of the first or second pins to the storage capacitor coupled to the other of the first or second pins.