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US 11,894,821 B2Granted
Scalable fir filter
AssigneeThe Boeing Company
InventorsKristine M. Skinner, Tyler J. Thrane, Jason A. Ching
Life of this patent
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Abstract
A Scalable Finite Impulse Response (“SFIR”) filter includes a pre-processing section, a post-processing section, and a finite impulse response (“FIR”) Matrix. The FIR Matrix is coupled to the pre-processing section and the post-processing section. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths. Each filter tap of the plurality of filter taps has at least a first input, a second input, a multiplexer coupled to the first input and the second input, and a first flip-flop coupled to an output of the multiplexer. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap of the plurality of filter taps.
Claims20
A Scalable Finite Impulse Response (“SFIR”) filter comprising:
- a pre-processing section;
- a post-processing section;
- and
- a finite impulse response (“FIR”) Matrix coupled to the pre-processing section and the post-processing section, wherein the FIR Matrix comprises:
- a plurality of filter taps, each filter tap of the plurality of filter taps having at least:
- a first input;
- a second input;
- a multiplexer coupled to the first input and the second input;
- a first flip-flop coupled to an output of the multiplexer;
- a second flip-flop;
- a multiplier coupled between the first flip-flop and an adder, the multiplier being directly coupled to the adder;
- the adder coupled between the second flip-flop and the multiplier, the adder receiving output directly from the second flip flop and the adder receiving output directly from the multiplier;
- and
- a coefficient section directly coupled to a first input of the multiplier, the first input of the multiplier coupled solely to the coefficient section, the coefficient section to solely provide a coefficient;
- and
- a plurality of signal paths arranged to allow re-configurable data throughput between each filter tap of the plurality of filter taps.
13 more elements
A Scalable Finite Impulse Response (“SFIR”) filter comprising:
- a pre-processing section;
- a post-processing section;
- and
- a finite impulse response (“FIR”) Matrix coupled to the pre-processing section and the post-processing section, wherein the FIR Matrix comprises:
- a plurality of filter taps, each filter tap of the plurality of filter taps having at least:
- a first input;
- a second input;
- a multiplexer coupled to the first input and the second input;
- a first flip-flop coupled to an output of the multiplexer;
- a second flip-flop;
- a multiplier coupled between the first flip-flop and an adder, the multiplier being directly coupled to the adder;
- the adder coupled between the second flip-flop and the multiplier, the adder receiving output directly from the second flip flop and the adder receiving output directly from the multiplier;
- and
- a plurality of signal paths arranged to allow re-configurable data throughput between each filter tap of the plurality of filter taps;
- wherein the plurality of filter taps comprises a first filter tap, a second filter tap, and a third filter tap, and wherein the second filter tap has a first input coupled to an output of the first filter tap and a second input coupled to an output of the third filter tap.
12 more elements
A Scalable Finite Impulse Response (“SFIR”) filter comprising:
- a pre-processing section;
- a post-processing section;
- and
- a finite impulse response (“FIR”) Matrix coupled to the pre-processing section and the post-processing section, wherein the FIR Matrix comprises:
- a plurality of filter taps, each filter tap of the plurality of filter taps having at least:
- a first input;
- a second input;
- a multiplexer coupled to the first input and the second input;
- a first flip-flop coupled to an output of the multiplexer;
- a second flip-flop;
- a multiplier coupled between the first flip-flop and an adder, the multiplier being directly coupled to the adder;
- the adder coupled between the second flip-flop and the multiplier, the adder receiving output directly from the second flip flop and the adder receiving output directly from the multiplier;
- and
- a plurality of signal paths arranged to allow re-configurable data throughput between each filter tap of the plurality of filter taps;
- wherein the plurality of filter taps comprises a first filter tap, a second filter tap, a third filter tap, and a fourth filter tap, and wherein the plurality of signal paths comprises:
- a first serial signal path from the first filter tap to the second filter tap;
- a second serial signal path from the second filter tap to the third filter tap;
- a first cross signal path from the first filter tap to the fourth filter tap;
- a second cross signal path from the third filter tap to the second filter tap;
- and
- a third serial signal path from the third filter tap to the fourth filter tap.
18 more elements
A Scalable Finite Impulse Response (“SFIR”) filter comprising:
- a pre-processing section;
- a post-processing section;
- and
- a finite impulse response (“FIR”) Matrix coupled to the pre-processing section and the post-processing section, wherein the FIR Matrix comprises:
- a plurality of filter taps, each filter tap of the plurality of filter taps having at least:
- a first input;
- a second input;
- a multiplexer coupled to the first input and the second input;
- a first flip-flop coupled to an output of the multiplexer;
- a second flip-flop;
- a multiplier coupled between the first flip-flop and an adder, the multiplier being directly coupled to the adder;
- the adder coupled between the second flip-flop and the multiplier, the adder receiving output directly from the second flip flop and the adder receiving output directly from the multiplier;
- and
- a plurality of signal paths arranged to allow re-configurable data throughput between each filter tap of the plurality of filter taps;
- wherein the plurality of signal paths are arranged to configure the SFIR filter into a one serial input four tap filter or a two parallel input two tap filter.
12 more elements
A Scalable Finite Impulse Response (“SFIR”) filter comprising:
- a pre-processing section;
- a post-processing section;
- and
- a finite impulse response (“FIR”) Matrix coupled to the pre-processing section and the post-processing section, wherein the FIR Matrix comprises:
- a plurality of filter taps, each filter tap of the plurality of filter taps having at least:
- a first input;
- a second input;
- a multiplexer coupled to the first input and the second input;
- a first flip-flop coupled to an output of the multiplexer;
- a second flip-flop;
- a multiplier coupled between the first flip-flop and an adder, the multiplier being directly coupled to the adder;
- the adder coupled between the second flip-flop and the multiplier, the adder receiving output directly from the second flip flop and the adder receiving output directly from the multiplier;
- and
- a plurality of signal paths arranged to allow re-configurable data throughput between each filter tap of the plurality of filter taps;
- wherein the SFIR filter is configured to operate as a complex FIR filter and comprises the pre-processing section configured as a fan-out device and the post-processing section configured as a summation device.
12 more elements
A Scalable Finite Impulse Response (“SFIR”) filter comprising:
- a pre-processing section;
- a post-processing section;
- and
- a finite impulse response (“FIR”) Matrix coupled to the pre-processing section and the post-processing section, wherein the FIR Matrix comprises:
- a plurality of filter taps, each filter tap of the plurality of filter taps having at least:
- a first input;
- a second input;
- a multiplexer coupled to the first input and the second input;
- a first flip-flop coupled to an output of the multiplexer;
- a second flip-flop;
- a multiplier coupled between the first flip-flop and an adder, the multiplier being directly coupled to the adder;
- the adder coupled between the second flip-flop and the multiplier, the adder receiving output directly from the second flip flop and the adder receiving output directly from the multiplier;
- and
- a plurality of signal paths arranged to allow re-configurable data throughput between each filter tap of the plurality of filter taps;
- wherein the SFIR filter is configured to operate as a decimator and comprises the pre-processing section configured as a re-order device and the post-processing section configured as a summation device.
12 more elements
A Scalable Finite Impulse Response (“SFIR”) filter comprising:
- a pre-processing section;
- a post-processing section;
- and
- a finite impulse response (“FIR”) Matrix coupled to the pre-processing section and the post-processing section, wherein the FIR Matrix comprises:
- a plurality of filter taps, each filter tap of the plurality of filter taps having at least:
- a first input;
- a second input;
- a multiplexer coupled to the first input and the second input;
- a first flip-flop coupled to an output of the multiplexer;
- a second flip-flop;
- a multiplier coupled between the first flip-flop and an adder, the multiplier being directly coupled to the adder;
- the adder coupled between the second flip-flop and the multiplier, the adder receiving output directly from the second flip flop and the adder receiving output directly from the multiplier;
- and
- a plurality of signal paths arranged to allow re-configurable data throughput between each filter tap of the plurality of filter taps;
- wherein the SFIR filter is configured to operate as an interpolator and comprises the pre-processing section configured as a fan-out device and the post-processing section configured as a re-order device.
12 more elements
A Scalable Finite Impulse Response (“SFIR”) filter comprising:
- means for pre-processing;
- means for post-processing;
- and
- a finite impulse response (“FIR”) filtering matrix coupled to the means for pre-processing and the means for post-processing, wherein the FIR filtering matrix comprises:
- a plurality of filter taps, each filter tap of the plurality of filter taps having at least:
- a first input;
- a second input;
- a multiplexer coupled to the first input and the second input;
- a first flip-flop coupled to an output of the multiplexer;
- a second flip-flop;
- a multiplier coupled between the first flip-flop and an adder, the multiplier being directly coupled to the adder;
- the adder coupled between the second flip-flop and the multiplier, the adder receiving output directly from the second flip flop and the adder receiving output directly from the multiplier;
- and
- a coefficient section directly coupled to a first input of the multiplier, the first input of the multiplier coupled solely to the coefficient section, the coefficient section to solely provide a coefficient;
- and
- a plurality of signal paths, wherein the plurality of signal paths comprises means to allow re-configurable data throughput between each filter tap of the plurality of filter taps.
13 more elements
An Application Specific Integrated Circuit (“ASIC”) comprising:
- a Scalable Finite Impulse Response (“SFIR”) filter comprising:
- a pre-processing section;
- a post-processing section;
- and
- a finite impulse response (“FIR”) Matrix coupled to the pre-processing section and the post-processing section, wherein the FIR Matrix comprises:
- a plurality of filter taps, each filter tap of the plurality of filter taps having at least:
- a first input;
- a second input;
- a multiplexer coupled to the first input and the second input;
- a first flip-flop coupled to an output of the multiplexer;
- a second flip-flop;
- a multiplier coupled between the first flip-flop and an adder, the multiplier being directly coupled to the adder;
- an adder coupled between the second flip-flop and the multiplier, the adder receiving output directly from the second flip flop and the adder receiving output directly from the multiplier;
- and
- a coefficient section directly coupled to a first input of the multiplier, the first input of the multiplier coupled solely to the coefficient section, the coefficient section to solely provide a coefficient;
- and
- a plurality of signal paths arranged to allow re-configurable data throughput between each filter tap of the plurality of filter taps.
14 more elements
Dependencies are inferred from the claim text.