Semiconductor device having nanosheet transistor and methods of fabrication thereof

A method for forming a semiconductor device structure, comprising:

• forming a sacrificial gate structure over a portion of first and second fin structures, each first and second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;
• forming a source/drain feature on opposite sides of the sacrificial gate structure, the source/drain feature being in contact with the plurality of first semiconductor layers of the first and second fin structures;
• removing the sacrificial gate structure and the plurality of second semiconductor layers to expose portions of each of the plurality of first semiconductor layers of the first and second fin structures;
• forming a dipole layer to surround exposed portions of each of the plurality of first semiconductor layers of the first and second fin structures, wherein the dipole layer comprises germanium;
• subjecting the dipole layer over the first and second fin structures to a thermal treatment such that portions of germanium in the dipole layer diffuse into and mix with each of the plurality of first semiconductor layers of the first and second fin structures to form an intermixed layer, wherein the intermixed layer has a Ge concentration profile gradually and continuously changed along a thickness of the intermixed layer;
• forming a capping layer to surround and in contact with the dipole layer;
• forming an interfacial layer (IL) to surround the capping layer;
• and
• forming a gate electrode layer to surround each of the plurality of first semiconductor layers of the first and second fin structures.

A method for forming a semiconductor device structure, comprising:

• forming a sacrificial gate structure over a portion of first and second fin structures, each first and second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;
• forming a source/drain feature on opposite sides of the sacrificial gate structure, the source/drain feature being in contact with the plurality of first semiconductor layers of the first and second fin structures;
• removing the sacrificial gate structure and the plurality of second semiconductor layers to expose portions of each of the plurality of first semiconductor layers of the first and second fin structures;
• forming a dipole layer to surround exposed portions of each of the plurality of first semiconductor layers of the first and second fin structures, wherein the dipole layer comprises germanium;
• subjecting the dipole layer to a thermal treatment such that portions of germanium in the dipole layer diffuse into and mix with each of the plurality of first semiconductor layers to form an intermixed layer, wherein the intermixed layer has a Ge concentration profile gradually and continuously changed along a thickness of the intermixed layer;
• forming a capping layer to surround and in contact with the dipole layer;
• forming a first interfacial layer to surround the capping layer;
• and
• forming a gate electrode layer to surround each of the plurality of first semiconductor layers of the first and second fin structures.