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US 11,894,459 B2Granted
Dual gate structures for semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Chih Su, Ruey-Hsin Liu, Pei-Lun Wang, Jia-Rui Lee, Jyun-Guan Jhou
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Abstract
The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.
Claims20
A method for forming a semiconductor structure, the method comprising:
- forming a channel region and a drift region in a substrate, wherein the channel region and the drift region are non-overlapping with each other;
- depositing a gate dielectric layer directly on top surfaces of the channel region, the drift region, and a portion of the substrate between the channel region and the drift region;
- depositing a gate material on the gate dielectric layer;
- etching the gate material to form a dual gate structure comprising:
- a first gate structure over the channel and drift regions;
- and
- a second gate structure over the drift region;
- etching the gate dielectric layer to form:
- a continuous layer under the first and second gate structures,
- a first sidewall of the gate dielectric layer aligned with an outer sidewall of the first gate structure, and
- a second sidewall of the gate dielectric layer aligned with an outer sidewall of the second gate structure, wherein the outer sidewalls of the first and second gate structures face opposite to each other;
- forming a first outer spacer on a first outer sidewall of the first gate structure and in physical contact with the top surface of the channel region;
- forming a second outer spacer on a second outer sidewall of the second gate structure and in physical contact with the top surface of the drift region;
- forming an inner spacer in contact with the first and second gate structures;
- etching the first gate structure to expose a top surface of the gate dielectric layer;
- and
- forming a metal gate structure with a bottom surface directly on the top surface of the gate dielectric layer and with a sidewall in physical contact with the first outer spacer.
14 more elements
A method, comprising:
- forming a channel region and a drift region;
- depositing a gate dielectric layer on top surfaces of the channel region and the drift region;
- forming a first gate structure on a top surface of the gate dielectric layer and over the channel and drift regions;
- forming a second gate structure on the top surface of the gate dielectric layer and over the drift region;
- etching the gate dielectric layer to form:
- a continuous layer under the first and second gate structures,
- a first sidewall of the gate dielectric layer aligned with an outer sidewall of the first gate structure, and
- a second sidewall of the gate dielectric layer aligned with an outer sidewall of the second gate structure, wherein the outer sidewalls of the first and second gate structures face opposite to each other;
- forming a first outer spacer on a first outer sidewall of the first gate structure and in physical contact with the top surface of the channel region;
- forming a second outer spacer on a second outer sidewall of the second gate structure and in physical contact with the top surface of the drift region;
- forming an inner spacer in contact with an inner sidewall of the first gate structure and an inner sidewall of the second gate structure;
- removing the first gate structure to expose the top surface of the gate dielectric layer;
- and
- forming a metal gate structure with a bottom surface directly on the top surface of the gate dielectric layer and with a sidewall in physical contact with the first outer spacer.
11 more elements
A method, comprising:
- forming a channel region and a drift region;
- depositing a gate dielectric layer on top surfaces of the channel region and the drift region;
- depositing a gate material on the gate dielectric layer;
- etching the gate material to form:
- a first gate structure over the channel and drift regions;
- and
- a second gate structure over the drift region, wherein inner sidewalls of the first and second gate structures are separated from each other by an opening over the gate dielectric layer;
- etching the gate dielectric layer to form:
- a continuous layer under the first and second gate structures,
- a first sidewall of the gate dielectric layer aligned with an outer sidewall of the first gate structure, and
- a second sidewall of the gate dielectric layer aligned with an outer sidewall of the second gate structure, wherein the outer sidewalls of the first and second gate structures face opposite to each other;
- forming a first outer spacer on a first outer sidewall of the first gate structure and in physical contact with the top surface of the channel region;
- forming a second outer spacer on a second outer sidewall of the second gate structure and in physical contact with the top surface of the drift region;
- etching the first gate structure to expose a top surface of the gate dielectric layer;
- depositing a work function metal layer with a bottom surface directly on the top surface of the gate dielectric layer and with a sidewall in physical contact with the first outer spacer;
- and
- depositing a gate electrode layer on the work function metal layer.
14 more elements
Dependencies are inferred from the claim text.