Semiconductor device, battery protection circuit, and power management circuit

A semiconductor device of chip-size package type that is face-down mountable, the semiconductor device comprising:

• a semiconductor layer;
• and
• N vertical MOS transistors in the semiconductor layer, where N is an integer greater than or equal to three, the N vertical MOS transistors including a first vertical MOS transistor, a second vertical MOS transistor, and a third vertical MOS transistor, wherein
• each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and a source pad electrically connected to a source electrode of the vertical MOS transistor,
• the semiconductor layer includes a semiconductor substrate,
• the semiconductor substrate functions as a common drain region for the N vertical MOS transistors,
• in a plan view of the semiconductor layer, the semiconductor device has a rectangular shape including a first outer peripheral side, a second outer peripheral side adjacent to the first outer peripheral side, a third outer peripheral side adjacent to the first outer peripheral side, and a fourth outer peripheral side opposing the first outer peripheral side,
• in a plan view of the semiconductor layer, the first vertical MOS transistor:
• has a polygonal shape including a first side whose entire length faces the first outer peripheral side, a second side whose entire length faces the second outer peripheral side and that is adjacent to the first side, and a third side whose entire length faces the third outer peripheral side and that is adjacent to the first side;
• and
• is arranged such that no other vertical MOS transistor among the N vertical MOS transistors is provided between the first outer peripheral side and the first side, between the second outer peripheral side and the second side, or between the third outer peripheral side and the third side,
• in a plan view of the semiconductor layer, the second vertical MOS transistor:
• has a polygonal shape including a fourth side whose entire length faces the second outer peripheral side, and a fifth side whose entire length faces the fourth outer peripheral side and that is adjacent to the fourth side;
• and
• is arranged such that no other vertical MOS transistor among the N vertical MOS transistors is provided between the second outer peripheral side and the fourth side or between the fourth outer peripheral side and the fifth side,
• in a plan view of the semiconductor layer, the third vertical MOS transistor:
• has a polygonal shape including a sixth side whose entire length faces the third outer peripheral side, and a seventh side whose entire length faces the fourth outer peripheral side and that is adjacent to the sixth side;
• and
• is arranged such that no other vertical MOS transistor among the N vertical MOS transistors is provided between the third outer peripheral side and the sixth side or between the fourth outer peripheral side and the seventh side,
• for each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor, and
• IM1>IM2=IM3 or IM1<IM2=IM3, where IM1 is the maximum specified current of the first vertical MOS transistor, IM2 is the maximum specified current of the second vertical MOS transistor, and IM3 is the maximum specified current of the third vertical MOS transistor.

A semiconductor device of chip-size package type that is face-down mountable, the semiconductor device comprising:

• a semiconductor layer;
• and
• N vertical transistors in the semiconductor layer, where N is an integer greater than or equal to three, the N vertical transistors including a first vertical transistor, a second vertical transistor, and a third vertical transistor, wherein
• each of the N vertical transistors includes, on an upper surface of the semiconductor layer, a control pad electrically connected to a control electrode that controls conduction of the vertical transistor and an external connection pad electrically connected to an external connection electrode through which the vertical transistor receives current from outside or outputs current outside,
• the semiconductor layer includes a semiconductor substrate,
• the semiconductor substrate includes one main surface on which the N vertical transistors are formed and an other main surface facing away from the one main surface, and the semiconductor device further includes a common electrode common to the N vertical transistors on the other main surface side of the semiconductor substrate,
• in a plan view of the semiconductor layer, the semiconductor device has a rectangular shape including a first outer peripheral side, a second outer peripheral side adjacent to the first outer peripheral side, a third outer peripheral side adjacent to the first outer peripheral side, and a fourth outer peripheral side opposing the first outer peripheral side,
• in a plan view of the semiconductor layer, the first vertical transistor:
• has a polygonal shape including a first side whose entire length faces the first outer peripheral side, a second side whose entire length faces the second outer peripheral side and that is adjacent to the first side, and a third side whose entire length faces the third outer peripheral side and that is adjacent to the first side;
• and
• is arranged such that no other vertical transistor among the N vertical transistors is provided between the first outer peripheral side and the first side, between the second outer peripheral side and the second side, or between the third outer peripheral side and the third side,
• in a plan view of the semiconductor layer, the second vertical transistor:
• has a polygonal shape including a fourth side whose entire length faces the second outer peripheral side, and a fifth side whose entire length faces the fourth outer peripheral side and that is adjacent to the fourth side;
• and
• is arranged such that no other vertical transistor among the N vertical transistors is provided between the second outer peripheral side and the fourth side or between the fourth outer peripheral side and the fifth side,
• in a plan view of the semiconductor layer, the third vertical transistor:
• has a polygonal shape including a sixth side whose entire length faces the third outer peripheral side, and a seventh side whose entire length faces the fourth outer peripheral side and that is adjacent to the sixth side;
• and
• is arranged such that no other vertical transistor among the N vertical transistors is provided between the third outer peripheral side and the sixth side or between the fourth outer peripheral side and the seventh side,
• for each of the N vertical transistors, a surface area of the vertical transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical transistor, and
• S1>S2=S3 or S1<S2=S3, where S1 is the surface area of the first vertical transistor in a plan view of the semiconductor layer, S2 is the surface area of the second vertical transistor in a plan view of the semiconductor layer, and S3 is the surface area of the third vertical transistor in a plan view of the semiconductor layer.

A semiconductor device of chip-size package type that is face-down mountable, the semiconductor device comprising:

• a semiconductor layer;
• and
• N vertical transistors in the semiconductor layer, where N is an integer greater than or equal to three, the N vertical transistors including a first vertical transistor, a second vertical transistor, and a third vertical transistor, wherein
• each of the N vertical transistors includes, on an upper surface of the semiconductor layer, a control pad electrically connected to a control electrode that controls conduction of the vertical transistor and an external connection pad electrically connected to an external connection electrode through which the vertical transistor receives current from outside or outputs current outside,
• the semiconductor layer includes a semiconductor substrate,
• the semiconductor substrate includes one main surface on which the N vertical transistors are formed and an other main surface facing away from the one main surface, and the semiconductor device further includes a common electrode common to the N vertical transistors on the other main surface side of the semiconductor substrate,
• in a plan view of the semiconductor layer, the semiconductor device has a rectangular shape including a first outer peripheral side, a second outer peripheral side adjacent to the first outer peripheral side, a third outer peripheral side adjacent to the first outer peripheral side, and a fourth outer peripheral side opposing the first outer peripheral side,
• in a plan view of the semiconductor layer, the first vertical transistor:
• has a polygonal shape including a first side whose entire length faces the first outer peripheral side, a second side whose entire length faces the second outer peripheral side and that is adjacent to the first side, and a third side whose entire length faces the third outer peripheral side and that is adjacent to the first side;
• and
• is arranged such that no other vertical transistor among the N vertical transistors is provided between the first outer peripheral side and the first side, between the second outer peripheral side and the second side, or between the third outer peripheral side and the third side,
• in a plan view of the semiconductor layer, the second vertical transistor:
• has a polygonal shape including a fourth side whose entire length faces the second outer peripheral side, and a fifth side whose entire length faces the fourth outer peripheral side and that is adjacent to the fourth side;
• and
• is arranged such that no other vertical transistor among the N vertical transistors is provided between the second outer peripheral side and the fourth side or between the fourth outer peripheral side and the fifth side,
• in a plan view of the semiconductor layer, the third vertical transistor:
• has a polygonal shape including a sixth side whose entire length faces the third outer peripheral side, and a seventh side whose entire length faces the fourth outer peripheral side and that is adjacent to the sixth side;
• and
• is arranged such that no other vertical transistor among the N vertical transistors is provided between the third outer peripheral side and the sixth side or between the fourth outer peripheral side and the seventh side,
• for each of the N vertical transistors, a surface area of the vertical transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical transistor, and
• IM1>IM2=IM3 or IM1<IM2=IM3, where IM1 is the maximum specified current of the first vertical transistor, IM2 is the maximum specified current of the second vertical transistor, and IM3 is the maximum specified current of the third vertical transistor.