Method of manufacturing a semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorLing-Yen Yeh
Life of this patent
Estimating the term…
Abstract
In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides.
Claims20
A semiconductor device, comprising:
- a plurality of semiconductor wires;
- a gate dielectric layer wrapping around each of the plurality of semiconductor wires;
- and
- a gate electrode layer disposed over the gate dielectric layer,
- wherein a cross sectional shape of an uppermost one of the plurality of semiconductor wires has a tear-drop shape and has a largest area among the plurality of semiconductor wires, and wherein a cross sectional shape of a bottommost one of the plurality of semiconductor wires has a smallest area among the plurality of semiconductor wires.
A semiconductor device, comprising:
- a plurality of semiconductor wires;
- a bottom fin structure protruding from a semiconductor substrate, over which the plurality of semiconductor wires are disposed;
- a gate dielectric layer wrapping around each of the plurality of semiconductor wires;
- a gate electrode layer disposed over the gate dielectric layer;
- a source/drain region which is a source/drain semiconductor fin structure;
- a source/drain epitaxial layer wrapping the source/drain semiconductor fin structure;
- an isolation insulating layer from which the source/drain semiconductor fin structure protrudes;
- and
- sidewall spacers disposed on opposite side faces of the gate electrode layer,
- wherein the bottom fin structure and the source/drain semiconductor fin structure are continuously formed of a same semiconductor material, wherein a cross sectional shape of an uppermost one of the plurality of semiconductor wires has a tear-drop shape and has a largest area among the plurality of semiconductor wires.
A semiconductor device, comprising:
- a plurality of semiconductor wires;
- a gate dielectric layer wrapping around each of the plurality of semiconductor wires;
- a gate electrode layer disposed over the gate dielectric layer;
- an isolation insulating layer from which a source/drain semiconductor fin structure protrudes;
- sidewall spacers disposed on opposite side faces of the gate electrode layer;
- and
- a dielectric layer, made of a different material than the gate dielectric layer and the sidewall spacers, disposed between the gate electrode layer and the isolation insulating layer,
- wherein the dielectric layer includes SiON or SiOC, and
- wherein a cross sectional shape of an uppermost one of the plurality of semiconductor wires has a tear-drop shape and has a largest area among the plurality of semiconductor wires.
Dependencies are inferred from the claim text.