Semiconductor arrangement and method of manufacture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYun-Chi Wu, Tsung-Yu Yang, Cheng-Bo Shu, Chien Hung Liu
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Abstract
A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.
Claims20
A semiconductor arrangement, comprising:
- a first transistor, comprising a first gate structure;
- and
- a second transistor, comprising a second gate structure, wherein the second gate structure contacts the first gate structure such that an interface is defined between the first gate structure and the second gate structure and a center of the second gate structure is laterally offset from a center of the first gate structure at the interface.
A method of forming a semiconductor arrangement, comprising:
- forming a gate dielectric layer over a semiconductor layer;
- forming a gate electrode layer over the gate dielectric layer;
- forming a first gate mask over the gate electrode layer, wherein:
- the first gate mask comprises a hard mask layer, a bottom antireflective coating layer over the hard mask layer, a planarization layer over the bottom antireflective coating layer, and a photoresist layer over the planarization layer;
- and
- etching the gate electrode layer using the first gate mask as an etch template to form a first gate electrode.
A method of forming a semiconductor arrangement, comprising:
- forming a gate dielectric layer over a semiconductor layer;
- forming a gate electrode layer over the gate dielectric layer;
- forming a first gate mask over the gate electrode layer;
- etching the gate electrode layer using the first gate mask as an etch template to form a first gate electrode;
- implanting a first dopant into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer;
- forming a first sidewall spacer adjacent the first gate electrode after implanting the first dopant;
- and
- implanting a second dopant using the first sidewall spacer and the first gate electrode as an implantation template to form a second doped region in the semiconductor layer, wherein:
- the first doped region extends to a first depth below a top surface of the semiconductor layer,
- the second doped region extends to a second depth below the top surface of the semiconductor layer, and
- the second depth is less than the first depth.
Dependencies are inferred from the claim text.