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US 11,894,424 B2Granted
Method for fabricating a field-effect transistor with size-reduced source/drain epitaxy
AssigneePostech Research and Business Development Foundation
InventorsRock Hyun Baek, Jun Sik Yoon, Jin Su Jeong, Seung Hwan Lee
Life of this patent
Estimating the term…
Abstract
Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.
Claims11
Method for manufacturing a fin field-effect transistor comprising:
- (a) forming a channel, a gate, and an insulating layer in a predetermined region of a substrate so that the insulating layer is formed from both sides of the gate on an upper portion of the substrate,
- (b) performing etching along side surfaces of the channel and the insulating layer so as to etch even an upper portion of one side of the substrate for forming source/drain regions, so that a designated region of the substrate is exposed and so that the insulating layer, patterned so as to wrap the exposed region of the substrate, is formed on the substrate, and
- (c) forming the source/drain regions, in which growth in a width direction (Y-axis direction) is restricted through a selective epitaxial growth process, in the exposed region of the substrate.
Dependencies are inferred from the claim text.