Contact resistance reduction in nanosheet device structure

An integrated circuit, comprising:

• one or more semiconductor devices, wherein at least one of the semiconductor devices comprises:
• a nanosheet field-effect transistor device disposed on a semiconductor substrate, wherein the nano sheet field-effect transistor device comprises:
• a plurality of nanosheet stack structures each comprising a plurality of semiconductor channel layers;
• a gate structure on the nanosheet stack structures;
• a gate sidewall spacer on the gate structure;
• a source/drain region in contact with sidewalls of the nanosheet stack structures and on a portion of the gate sidewall spacer to define a trench between opposing sidewalls;
• and
• a metal-based material disposed in the trench, on a top surface of the source/drain region and on the gate sidewall spacer;
• wherein the source/drain region is disposed on the sidewalls of the nanosheet stack structures and on a portion of an oxide layer disposed over a portion of the semiconductor substrate;
• wherein the source/drain region has a uniform thickness along the sidewalls of the nanosheet stack structures and on the portion of the gate sidewall spacer;
• and
• wherein the trench extends through the source/drain region to the oxide layer.

A semiconductor device, comprising:

• a nanosheet field-effect transistor device disposed on a semiconductor substrate, wherein the nanosheet field-effect transistor device comprises:
• a nanosheet stack structure comprising a semiconductor channel layer;
• a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure;
• and
• a metal-based source/drain contact material disposed in a trench in the source/drain region;
• wherein the source/drain region has a uniform thickness along the end portion of the semiconductor channel layer of the nanosheet stack structure;
• wherein the source/drain region is disposed on the end portion of the semiconductor channel layer and on a portion of an oxide layer disposed over a portion of the semiconductor substrate;
• and
• wherein the trench extends through the source/drain region to the oxide layer.