US 11,894,417 B2Granted

Method of fabricating a perovskite-material based trench capacitor using rapid thermal annealing (RTA) methodologies

AssigneeKepler Computing Inc.

InventorsNiloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren, FNU Atiquzzaman, Gabriel Antonio Paulius Velarde, Noriyuki Sato, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh, Sasikanth Manipatruni

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Abstract

A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Claims20

Dependent claims

A method of fabricating a device structure, the method comprising:

forming an electrode structure in a memory region by a first process comprising:
etching a first opening in an etch stop layer and exposing a conductive interconnect below the etch stop layer;
depositing a first conductive material on the conductive interconnect;
and
depositing a first conductive hydrogen barrier layer in the first conductive material;
and
depositing a dielectric on the etch stop layer;
forming a trench capacitor by a second process comprising:
forming a trench in the dielectric, the trench exposing at least a portion of the electrode structure;
depositing a first electrode layer on a base and on sidewalls of the trench, wherein the first electrode layer comprises a first conductive nonlinear polar material, the first conductive nonlinear polar material comprising a first grain length;
depositing a dielectric layer comprising a perovskite material on the first electrode layer, the perovskite material comprising a second grain length;
depositing a second electrode layer on the dielectric layer, wherein the second electrode layer comprises a second conductive nonlinear polar material, the second conductive nonlinear polar material comprising a third grain length that is substantially equal to the first grain length;
and
performing a post deposition anneal (PDA) for a duration of less than 60 seconds at temperatures below 1300 degrees Celsius, wherein the PDA modifies the first conductive nonlinear polar material to have a first new grain length which is a factor of 3 larger than the first grain length, wherein the PDA modifies the perovskite material to have a second new grain length which is a factor of 3 larger than the second grain length, and wherein the PDA modifies the second conductive nonlinear polar material to have a third new grain length which is a factor of 3 larger than the third grain length;
and
forming a via electrode on the trench capacitor by a third process comprising:
depositing a second conductive hydrogen barrier layer on the second electrode layer;
and
depositing a second conductive material on the second conductive hydrogen barrier layer.

16 more elements

A method of fabricating a device structure, the method comprising:

fabricating a transistor, the method comprising:
forming a fin structure in a substrate by patterning the substrate;
forming an isolation adjacent to the fin structure;
forming an epitaxial source structure, an epitaxial drain structure and a channel in the fin structure;
performing an activation anneal at a temperature of at least 600 degrees Celsius;
forming a gate on the channel;
and
forming a first contact on the epitaxial drain structure and a second contact on the gate;
forming a conductive interconnect on the first contact or on the second contact;
forming an electrode structure by a first process comprising:
etching a first opening in an etch stop layer and exposing at least a portion of the conductive interconnect;
depositing a first conductive hydrogen barrier layer in the first opening;
depositing a first conductive material on the first conductive hydrogen barrier layer;
and
depositing a dielectric on the etch stop layer;
forming a trench capacitor by a second process comprising:
forming a trench in the dielectric, the trench exposing at least a portion of the electrode structure;
depositing a first electrode layer on a base and on sidewalls of the trench, wherein the first electrode layer comprises a first conductive nonlinear polar material, the first conductive nonlinear polar material comprising a first grain length;
depositing a dielectric layer comprising a perovskite material on the first electrode layer, the perovskite material comprising a second grain length;
depositing a second electrode layer on the dielectric layer, wherein the second electrode layer comprises a second conductive nonlinear polar material, the second conductive nonlinear polar material comprising a third grain length that is substantially equal to the first grain length;
and
performing a post deposition anneal (PDA) for a duration of less than 60 seconds at temperatures below 1300 degree Celsius, wherein the PDA modifies the first conductive nonlinear polar material to have a first new grain length which is a factor of 3 larger than the first grain length, wherein the PDA modifies the perovskite material to have a second new grain length which is a factor of 3 larger than the second grain length, and wherein the PDA modifies the second conductive nonlinear polar material to have a third new grain length which is a factor of 3 larger than the third grain length;
and
forming a via electrode on the trench capacitor by a third process comprising:
depositing a second conductive hydrogen barrier layer on the second electrode layer;
and
depositing a second conductive material on the second conductive hydrogen barrier layer.

24 more elements

A method of fabricating a device structure, the method comprising:

fabricating a transistor, the method comprising:
forming a fin structure in a substrate by patterning the substrate;
forming an isolation adjacent to the fin structure;
forming an epitaxial source structure, an epitaxial drain structure and a channel in the fin structure;
performing an activation anneal at a temperature of at least 600 degrees Celsius;
forming a gate on the channel;
and
forming a first contact on the epitaxial drain structure and a second contact on the gate;
forming a conductive interconnect on the first contact or on the second contact;
forming an electrode structure by a first process comprising:
etching a first opening in an etch stop layer and exposing at least a portion of the conductive interconnect;
depositing a first conductive hydrogen barrier layer in the first opening;
depositing a first conductive material on the first conductive hydrogen barrier layer;
and
depositing a dielectric on the etch stop layer;
forming a trench capacitor by a second process comprising:
forming a trench in the dielectric, the trench exposing at least a portion of the electrode structure;
depositing a first electrode layer on a base and on sidewalls of the trench, wherein the first electrode layer comprises a first conductive nonlinear polar material, the first conductive nonlinear polar material comprising a first grain length;
depositing a dielectric layer comprising a perovskite material on the first electrode layer, the perovskite material comprising a second grain length;
performing a post deposition anneal (PDA) for a duration of less than 60 seconds at temperatures below 1300 degree Celsius, wherein the PDA modifies the first conductive nonlinear polar material to have a first new grain length which is a factor of 3 larger than the first grain length, wherein the PDA modifies the perovskite material to have a second new grain length which is a factor of 3 larger than the second grain length;
and
depositing a second electrode layer on the dielectric layer, wherein the second electrode layer comprises a second conductive nonlinear polar material, the second conductive nonlinear polar material comprising a third grain length that is less the first grain length;
and
forming a via electrode on the trench capacitor by a third process comprising:
depositing a second conductive hydrogen barrier layer on the second electrode layer;
and
depositing a second conductive material on the second conductive hydrogen barrier layer.

24 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/649,899Filed 3 Feb 2022 · continuation
Priority: 31 Jan 2022
Published: US 2023/0246062 A13 Aug 2023
Granted: 6 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 1/682
Capacitors having no potential barriers: having dielectrics comprising perovskite structures
H10D 1/688
Having dielectrics comprising perovskite structures: comprising barrier layers to prevent diffusion of hydrogen or oxygen
H10B 53/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the memory core region
H10D 1/694
Electrodes: comprising noble metals or noble metal oxides

Family

Application17/649,534Parent of this continuation · filed 31 Jan 2022
US 2023/0246064 A1Pre-grant publication · published 3 Aug 2023
US 12,094,923 B2Related patent
US 2023/0246062 A1Published application
US 11,894,417 B2This patent

From the US filing history. Foreign family members aren’t listed.