US 11,894,383 B2Granted

Staking nanosheet transistors

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsPochun Wang, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien

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Abstract

A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

Claims20

Dependent claims

A method for manufacturing a semiconductor structure, comprising:

forming a fin structure over a substrate;
forming a source/drain of a first transistor, a source/drain of a second transistor and a first semiconductive component in the fin structure of the substrate at a first elevation, wherein the first semiconductive component is adjacent to the source/drain of the second transistor;
forming a gate structure of the first transistor and a gate structure of the second transistor surrounding the fin structure of the substrate, wherein the source/drain and the gate structure of the first transistor are arranged along a horizontal direction, and the source/drain and the gate structure of the second transistor are arranged along the horizontal direction;
forming a source/drain of a third transistor, a source/drain of a fourth transistor, and a second semiconductive component in the fin structure of the substrate at a second elevation, wherein the second semiconductive component is adjacent to the source/drain of the third transistor, and the second elevation is different from the first elevation;
forming a gate structure of the third transistor and a gate structure of the fourth transistor surrounding the fin structure of the substrate,
wherein the source/drain and the gate structure of the third transistor are arranged along the horizontal direction, the source/drain and the gate structure of the fourth transistor are arranged along the horizontal direction, the second transistor is vertically aligned with the third transistor, the first semiconductive component is vertically aligned with the source/drain of the fourth transistor, the second semiconductive component is vertically aligned with the source/drain of the first transistor, and a gate structure between the second semiconductive component and the source/drain of the third transistor is absent.

3 more elements

A method of manufacturing a semiconductor structure, comprising:

receiving a substrate;
forming a fin structure over the substrate, wherein the fin structure includes a lower portion and an upper portion over the lower portion, the lower portion defines a first active layer, and the upper portion defines a second active layer;
forming a plurality of first source/drain structures, disposed in the first active layer;
forming a plurality of second source/drain structures, disposed in the second active layer and aligned with the plurality of first source/drain structures respectively;
forming a first gate structure, disposed around or over the first active layer and between the plurality of the first source/drain structures, and separated from the second active layer;
forming a second gate structure, continuously disposed across the first active layer and the second active layer, and disposed between the plurality of first source/drain structures in the first active layer and between the plurality of second source/drain structures in the second active layer;
and
forming a third gate structure, disposed around or over the second active layer between the plurality of the second source/drain structures, and separated from the first active layer.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/829,330Filed 31 May 2022 · division
Priority: 27 Sep 2019
Published: US 2022/0293638 A115 Sep 2022
Granted: 6 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

H10D 86/215
The substrates comprising an insulating layer on a semiconductor body, e.g. SOI: comprising FinFETs
H10W 20/021
Manufacture or treatment: of interconnections within wafers or substrates
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/501
Field-effect transistors [FET]: fETs having stacked nanowire, nanosheet or nanoribbon channels

Family

Application62/907,426Us provisional application · filed 27 Sep 2019
Application16/927,740Parent of this division · filed 13 Jul 2020
US 2022/0293638 A1Pre-grant publication · published 15 Sep 2022
US 11,362,110 B2Parent of this division
US 2021/0098500 A1Published application
US 11,894,383 B2This patent

From the US filing history. Foreign family members aren’t listed.