Semiconductor devices and method of manufacturing the same

A semiconductor device, comprising:

• a first transistor in a first region of a substrate and a second transistor in a second region of the substrate,
• wherein the first transistor comprises:
• a plurality of first channel regions being spaced apart from each other in a first direction perpendicular to a top surface of the substrate;
• a first gate electrode surrounding the plurality of first channel regions;
• a first external insulating spacer on upper sidewalls of the first gate electrode,
• a first source/drain region connected to an edge of the plurality of first channel regions, the first source/drain region contacting the first external insulating spacer, the first source/drain region including stacking faults or dislocations therein;
• and
• a plurality of inner-insulating spacers between the first gate electrode and the first source/drain region and between two adjacent ones of the plurality of first channel regions, the plurality of inner-insulating spacers having a curved sidewall facing the first gate electrode,
• the second transistor comprises:
• a plurality of second channel regions being spaced apart from each other in the first direction;
• a second gate electrode surrounding the plurality of second channel regions;
• a second external insulating spacer on upper sidewalls of the second gate electrode;
• and
• a second source/drain region connected to an edge of the plurality of second channel regions, the second source/drain region contacting the second external insulating spacer, the second source/drain region including a plurality of protrusion portions facing the second gate electrode, the plurality of protrusion portions being disposed between two adjacent ones of the plurality of second channel regions, and
• the first gate electrode includes a plurality of first sub-gate electrodes between two adjacent ones of the plurality of first channel regions, each of the plurality of first sub-gate electrodes includes a tail portion at an upper edge and a lower edge of the first sub-gate electrodes, the tail portion conforms to a shape of the curved sidewall of the plurality of inner-insulating spacers,
• wherein the second gate electrode includes a plurality of second sub-gate electrodes between two adjacent second channel regions of the plurality of second channel regions, and
• wherein a separation distance between the first source/drain region and the plurality of first sub-gate electrodes is greater than a separation distance between the second source/drain region and the plurality of second sub-gate electrodes.