Semiconductor structure and manufacturing method thereof

A method of manufacturing a semiconductor structure, comprising:

• providing a substrate, wherein an isolation structure is formed in the substrate to separate a first active region and a second active region;
• forming a dielectric layer, wherein the dielectric layer above the first active region is used as a first dielectric layer, and the dielectric layer above the second active region is used as a second dielectric layer, and forming a first initial work function layer on the second dielectric layer;
• forming a first sidewall isolation layer on a side of the first dielectric layer close to the second dielectric layer, and forming a second sidewall isolation layer on a sidewall of the first initial work function layer close to the first dielectric layer;
• forming a second initial work function layer, wherein the second initial work function layer on the first dielectric layer is used as a first work function layer, the first initial work function layer and the second initial work function layer on the first initial work function layer are used as a second work function layer;
• and
• forming a conductive layer, wherein the conductive layer on the first work function layer is used as a first conductive layer, and the conductive layer on the second work function layer is used as a second conductive layer;
• wherein the first sidewall isolation layer covers a sidewall of the first work function layer, the first sidewall isolation layer and the second sidewall isolation layer are formed in a same process step, and the forming the first sidewall isolation layer and forming the second sidewall isolation layer comprises:
• forming an initial isolation layer on the first dielectric layer and the first initial work function layer;
• and
• partially etching the initial isolation layer, and exposing a part of the first dielectric layer and an upper surface of the first initial work function layer, so as to form the first sidewall isolation layer and the second sidewall isolation layer.

A semiconductor structure, comprising a substrate, and an NMOS transistor and a PMOS transistor that are located on the substrate, wherein

• the NMOS transistor comprises:
• a first dielectric layer, located on the substrate;
• a first work function layer, located on the first dielectric layer;
• and
• a first conductive layer, located on the first work function layer;
• and
• the PMOS transistor comprises:
• a second dielectric layer, located on the substrate;
• a second work function layer, located on the second dielectric layer;
• and
• a second conductive layer, located on the second work function layer;
• at least one of:
• the first work function layer is provided with a first sidewall isolation layer on a side facing the second work function layer, or
• the second work function layer is provided with a second sidewall isolation layer on a side facing the first work function layer,
• an isolation structure is formed in the substrate, so as to separate a first active region and a second active region in the substrate for the NMOS transistor and the PMOS transistor respectively, and
• at least one of the NMOS transistor or the PMOS transistor covers a part of the isolation structure.