Integrated circuit including dipole incorporation for threshold voltage tuning in transistors

A method, comprising:

• forming first semiconductor nanosheets of a first gate all around transistor of an integrated circuit;
• forming second semiconductor nanosheets of a second gate all around transistor of the integrated circuit;
• depositing an interfacial dielectric layer on the first and second semiconductor nanosheets;
• depositing a dipole-inducing layer on the interfacial dielectric layer on the first and second semiconductor nanosheets;
• covering the dipole-inducing layer on the first semiconductor nanosheets with a mask layer;
• and
• exposing the second semiconductor nanosheets by removing the dipole-inducing layer and the interfacial dielectric layer from the second semiconductor nanosheets while the dipole-inducing layer on the first semiconductor nanosheets is covered by the mask layer.

An integrated circuit, comprising:

• a first gate all around transistor including:
• a plurality of first semiconductor nanosheets corresponding to channel regions of the first gate all around transistor;
• a first interfacial dielectric layer positioned on the first semiconductor nanosheets;
• a dipole layer positioned on the first interfacial dielectric layer and including dipole material;
• and
• a first high-K dielectric layer positioned on the dipole layer;
• and
• a second gate all around transistor including:
• a plurality of second semiconductor nanosheets corresponding to channel regions of the second gate all around transistor;
• a second interfacial dielectric layer positioned on the second semiconductor nanosheets;
• and
• a second high-K dielectric layer positioned directly on the second interfacial dielectric layer, wherein a concentration of the dipole material is zero in the second interfacial dielectric layer and the second high-K dielectric layer, wherein a distribution of dipole dopants in the first interfacial dielectric layer and a distribution of dipole dopants in the first high-K dielectric layer are arranged to mirror symmetrically along a central line between the first interfacial dielectric layer and the first high-K dielectric layer.