System-level packaging structure and method for LED chip

A System-in-Package (SiP) structure for a light emitting diode (LED) chip, comprising:

• a heat sink structure;
• a first chip, formed on the heat sink structure;
• a connecting pillar structure, formed on the first chip to electrically lead out the first chip;
• a first packaging layer, formed on the first chip, wherein the first packaging layer covers the connecting pillar structure, and wherein the first chip, the connecting pillar structure, and the first packaging layer constitute a first-chip initial packaging structure;
• a second packaging layer, formed on the heat sink structure, and covering the first-chip initial packaging structure;
• a rewiring layer, formed on the second packaging layer and the first-chip initial packaging structure, wherein the rewiring layer is electrically connected to the connecting pillar structure;
• an LED chip, formed on a side of the rewiring layer away from the first-chip initial packaging structure;
• a printed circuit board (PCB), electrically connected by a metal lead wire to a side of the rewiring layer with the LED chip formed thereon;
• a third packaging layer, formed at least around the LED chip;
• wherein an upper surface of the first packaging layer is flush with an upper surface of the second packaging layer, and wherein the first packaging layer exposes the connecting pillar structure, wherein a plurality of metal bumps are formed between the LED chip and the rewiring layer to electrically connect the LED chip and the rewiring layer, and wherein the third packaging layer is further formed among the plurality of metal bumps at a bottom of the LED chip.

A system-level packaging method for a light emitting diode (LED) chip, comprising:

• providing a chip wafer, comprising a first surface and a second surface opposite to each other, wherein the chip wafer comprises a plurality of first chips;
• forming a plurality of connecting pillar structures on the first surface of the chip wafer to electrically lead out the first chips;
• forming a first packaging layer on the first surface of the chip wafer, wherein the first packaging layer covers the connecting pillar structures;
• cutting the chip wafer to form a plurality of first-chip initial packaging structures, wherein the plurality of first chips and the plurality of connecting pillar structures are arranged in respective one of the plurality of first chips, and wherein the first packaging layer covers the plurality of connecting pillar structures;
• providing a supporting substrate, forming a separation layer on the supporting substrate, and attaching second surfaces of the plurality of first-chip initial packaging structures on the separation layer;
• forming a second packaging layer on the separation layer, wherein the second packaging layer covers the plurality of first-chip initial packaging structures, and thinning the second packaging layer to expose the connecting pillar structures;
• preparing a rewiring layer on the second packaging layer, wherein the rewiring layer is electrically connected to the plurality of connecting pillar structures;
• peeling off the supporting substrate using the separation layer to expose the second surfaces of the first-chip initial packaging structures, and performing cutting to obtain first-chip intermediate packaging structures;
• providing an LED chip and attaching the LED chip on a side of the rewiring layer away from the first-chip initial packaging structures, to obtain an integrated chip packaging structure;
• forming the integrated chip packaging structure on a heat sink structure and electrically connecting the side of the rewiring layer with the LED chip formed thereon to a printed circuit board (PCB) by a metal lead wire;
• forming a third packaging layer at least around the LED chip to obtain a System-in-Package (SiP) structure for an LED chip;
• wherein the PCB is formed on the heat sink structure and is located on a side portion of the integrated chip packaging structure, and the third packaging layer is further formed above the PCB and the rewiring layer and covers the metal lead wire;
• and
• wherein a thermal adhesive layer is further formed between the integrated chip packaging structure and the heat sink structure.