Wafer level package
AssigneeSamsung Electronics Co., Ltd.
InventorsJinwoo Park, Jungho Park, Dahye Kim, Minjun Bae
Life of this patent
Estimating the term…
Abstract
Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.
Claims18
A package comprising:
- a semiconductor chip on a package substrate, the package substrate including a trench having a line shape, the trench extending in a first direction along a first side surface of the semiconductor chip on the package substrate;
- and
- an underfill filling a space between the package substrate and the semiconductor chip, the underfill filling the trench,
- wherein the trench is disposed on a portion of the package substrate to overlap with at least a portion of the semiconductor chip in a second direction perpendicular to the first direction.
A package comprising:
- a semiconductor chip;
- a substrate, the semiconductor chip being mounted on the substrate, the substrate including at least one trench each having a line shape, the trench extending in a first direction along a first side surface of the semiconductor chip;
- an underfill filling a space between the substrate and the semiconductor chip and the at least one trench, the underfill covering side surfaces of the semiconductor chip;
- and
- a sealant covering and sealing the semiconductor chip and the underfill,
- wherein the at least one trench is disposed on a portion of the substrate to overlap with at least a portion of the semiconductor chip in a second direction perpendicular to the first direction.
A package comprising:
- a semiconductor chip;
- a substrate, the substrate including a first trench having a line shape, the first trench extending in a first direction along a first side surface of the semiconductor chip, the semiconductor chip being on the substrate;
- a chip stack structure on the substrate and having at least one memory chip, the semiconductor chip being spaced apart from the chip stack structure;
- and
- an underfill filling a space between the substrate and the semiconductor chip and, the underfill filling the first trench,
- wherein the first trench is disposed on a portion of the substrate to overlap with at least a portion of the semiconductor chip in a second direction perpendicular to the first direction.
Dependencies are inferred from the claim text.