US 11,894,329 B2 · Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars

Abstract

Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

Claims12

Dependent claims

A semiconductor die comprising:

a plurality of first conductive structures in a region of the semiconductor die, the first conductive structures configured to be electrically floating;
and
a plurality of second conductive structures attached to corresponding bond pads of the semiconductor die, wherein:
the first and second conductive structures have a common metallic component;
and
first heights of the first conductive structures are less than second heights of the second conductive structures.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/809,224Filed 27 Jun 2022 · division

Priority

30 Jun 2020

Published

US 2022/0328442 A113 Oct 2022

Granted

6 Feb 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10W 72/20
Interconnections or connectors in packages: bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
H10W 72/012
Manufacture or treatment: of bump connectors, dummy bumps or thermal bumps
H10W 72/01204
Of bump connectors, dummy bumps or thermal bumps: using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
H10W 72/01208
Of bump connectors, dummy bumps or thermal bumps: using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks

Family

Application16/916,325Parent of this division · filed 30 Jun 2020

US 2022/0328442 A1Pre-grant publication · published 13 Oct 2022

US 11,404,390 B2Parent of this division

US 2021/0407944 A1Published application

US 11,894,329 B2This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars

Life of this patent

Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars

Life of this patent

Abstract

Claims12