Semiconductor device with edge-protecting spacers over bonding pad
AssigneeNanya Technology Corporation
InventorJung-Hsing Chien
Life of this patent
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Abstract
The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.
Claims12
A semiconductor device, comprising:
- a bonding pad disposed over a semiconductor substrate;
- a first spacer disposed over a top surface of the bonding pad;
- a dielectric liner disposed between the first spacer and the bonding pad;
- a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide;
- a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad;
- a second spacer disposed over a sidewall of the bonding pad and conformally covering the first spacer;
- a first passivation layer covering the second spacer, wherein the first spacer is in direct contact with the first passivation layer;
- and
- a second passivation layer between the first passivation layer and the bonding pad, wherein the second spacer is covered by the second passivation layer, and a portion of the conductive bump is surrounded by the first passivation layer and the second passivation layer.
A semiconductor device, comprising:
- a bonding pad disposed over a semiconductor substrate;
- a first upper spacer disposed over a top surface of the bonding pad;
- a second upper spacer disposed over the first upper spacer and conformally covering the first upper spacer;
- a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide;
- and
- a conductive bump disposed over the first upper spacer and the second upper spacer, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.
Dependencies are inferred from the claim text.