Multi-metal contact structure
AssigneeAdeia Semiconductor Bonding Technologies Inc.
InventorsRajesh Katkar, Cyprian Emeka Uzoh
Life of this patent
Estimating the term…
Abstract
A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.
Claims20
A method comprising:
- providing a substrate having a recess or opening extending from a first surface of the substrate, at least a portion of the first surface of the substrate having a planarized topography;
- disposing a first conductive material having a first melting point within the recess or opening and forming a first portion of an interconnect structure of the substrate;
- and
- disposing a second conductive material having a second melting point different from the first melting point within the recess or opening and at least partially surrounded by the first conductive material, the second conductive material forming a second portion of the interconnect structure of the substrate, the second portion of the interconnect structure comprising a plurality of conductive portions extending normal to the plane of the substrate;
- and
- providing a barrier layer between the substrate and the first conductive material.
The method of claim I, further comprising disposing a layer of the first conductive material over an exposed surface of the second portion of the interconnect structure.
The method of claim I. further comprising disposing one or more additional conductive materials having one or more additional melting points different from the first melting point and the second melting point within the recess or opening and forming one or more additional portions of the interconnect structure of the substrate.
A method, comprising:
- providing a microelectronic component comprising:
- providing a first substrate having a recess or opening extending from a first surface of the first substrate, at least a portion of the first surface of the first substrate having a planarized topography;
- disposing a first conductive material having a first melting point within the recess or opening, extending normal to a plane of the first substrate and forming a first portion of a first interconnect structure of the microelectronic component;
- disposing a second conductive material having a second melting point different from the first melting point within the recess or opening, extending normal to the plane of the first substrate and forming a second portion of the first interconnect structure of the microelectronic component, the second portion of the first interconnect structure comprising a plurality of conductive portions at least partially surrounded by the first conductive material;
- and
- bonding a second interconnect structure of a second substrate to the first interconnect structure by at least one of a direct bond of an insulator material to another insulator material without an adhesive or by a metal to metal diffusion bond, thereby forming one of an electrical contact pad or a via with the first interconnect structure and the second interconnect structure.
A method comprising:
- providing a substrate having a recess or opening extending from a first surface of the substrate, at least a portion of the first surface of the substrate having a planarized topography;
- disposing a first conductive material having a first coefficient of thermal expansion (CTE) within the recess or opening and forming a first portion of an interconnect structure, the first portion of the interconnect structure extending normal to a plane of the substrate;
- disposing a second conductive material having a second CTE different from the first CTE within the recess or opening, the second conductive material forming a second portion of the interconnect structure, the second portion of the interconnect structure comprising a plurality of conductive portions extending normal to the plane of the substrate, the first conductive material at least partially surrounding the second conductive material;
- and
- disposing a barrier layer between the substrate and the first conductive material.
A method of fabricating a microelectronic component comprising:
- forming a recess or opening in a surface of a substrate;
- disposing a first conductive material having a first coefficient of theuiial expansion (CTE) within the recess or opening, the first conductive material at least partially filling the recess or opening and forming a first portion of an interconnect structure of the microelectronic component;
- disposing a second conductive material having a second CTE different from the first CTE within the recess or opening and forming a second portion of the interconnect structure of the microelectronic component;
- and
- planarizing the surface of the substrate, the first conductive material, and the second. conductive material and forming a planar bonding surface comprising the first portion and the second portion of the interconnect stricture and a planar dielectric surface.
Dependencies are inferred from the claim text.