Fan-out semiconductor package

A fan-out semiconductor package, comprising:

• a molded layer including first and second surfaces opposite to each other;
• an interconnector in the molded layer, the interconnector including a metal ball that has a full spherical shape;
• a semiconductor chip in the molded layer and spaced apart from the interconnector;
• a first redistribution layer including a first line wiring and a first via on the first surface of the molded layer;
• and
• a second redistribution layer on the second surface of the molded layer and including a second line wiring and a second via,
• wherein:
• the interconnector is between the first via and the second via and connected to the first via and the second via,
• an interface between the first via and the interconnector is a curved surface such that the first via has a rounded concavity that is complementary to the full spherical shape of the interconnector, and an interface between the second via and the interconnector is a curved surface such that the second via has a rounded concavity that is complementary to the full spherical shape of the interconnector.

A fan-out semiconductor package, comprising:

• a first redistribution layer including a first line wiring and a first via connected to the first line wiring;
• a first semiconductor chip on the first redistribution layer;
• an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip;
• a molded layer covering the interconnector and covering side surfaces of the first semiconductor chip;
• a second redistribution layer on the molded layer, the second redistribution layer including a second line wiring and a second via connected to the second line wiring;
• and
• a semiconductor package that includes a second semiconductor chip on the second redistribution layer and connected to the second line wiring,
• wherein:
• the interconnector includes a metal ball that has a full spherical shape,
• the first via is in contact with the interconnector,
• the second via is in contact with the interconnector,
• a part of the second via is inside the molded layer,
• the first semiconductor chip is electrically connected to the second semiconductor chip through the first line wiring, the first via, the interconnector, the second via, and the second line wiring,
• an interface between the first via and the interconnector is a curved surface such that the first via has a rounded concavity that is complementary to the full spherical shape of the interconnector, and
• an interface between the second via and the interconnector is a curved surface such that the second via has a rounded concavity that is complementary to the full spherical shape of the interconnector.