Semiconductor package and method of manufacturing the same

A substrate, comprising:

• a dielectric layer, having a first surface and a second surface opposite to the first surface, the dielectric layer defining a die region and a peripheral region adjoining to the die region;
• a first conductive via located in the peripheral region and extending between the first surface and the second surface, the first conductive via comprising a first pattern;
• a second conductive via located in the die region and extending between the first surface and the second surface;
• and
• a third conductive via located in the peripheral region and extending between the first surface and the second surface, the third conductive via comprising a third pattern:
• wherein the first pattern comprises at least two first geometric centers corresponding to at least two first geometric patterns, respectively, and wherein the third pattern comprises at least two third geometric centers corresponding to at least two third geometric patterns, respectively, and
• wherein a first imaginary line connecting the at least two first geometric centers is non-parallel to a second imaginary line connecting the at least two third geometric centers.

A substrate, comprising:

• a first dielectric layer, having a first surface and a second surface opposite to the first surface;
• a first conductive via extending between the first surface and the second surface of the first dielectric layer and including a first bottom surface exposed from the second surface of the first dielectric layer, the first bottom surface of the first conductive via including a first recess surface, the first recess surface including a first curved surface, the first conductive via comprising a first pattern, wherein the first pattern comprises at least two geometric centers corresponding to at least two geometric patterns, respectively;
• a second dielectric layer, having a first surface and a second surface opposite to the first surface;
• a second conductive via under the first dielectric layer and extending between the first surface and the second surface of the second dielectric layer, the second conductive via including a second top surface facing the conductive via and a second bottom surface opposite to the second top surface, the second bottom surface of the second conductive via including a second recess surface, the second recess surface including a second curved surface;
• and
• a third conductive via under the first dielectric layer and extending between the first surface and the second surface of the second dielectric layer, wherein a first portion of the second conductive via is directly connected to the third conductive via, and a second portion of the second conductive via is separated from the third conductive via through the second dielectric layer.