Semiconductor memory device and method of manufacturing semiconductor memory device
AssigneeSK hynix Inc.
InventorNam Jae Lee
Life of this patent
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Abstract
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.
Claims20
A semiconductor memory device, comprising:
- a source structure;
- a stacked conductive layer overlapping with the source structure;
- a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer;
- a stacked insulating layer disposed between the first select conductive layer and the stacked conductive layer and between the second select conductive layer and the stacked conductive layer;
- a first slit structure and a second slit structure passing through the stacked conductive layer and the stacked insulating layer;
- and
- a separation insulating structure passing through the source structure,
- wherein the first and second slit structures and the separation insulating structure are disposed between the first select conductive layer and the second select conductive layer, and
- wherein the separation insulating structure is disposed between the first slit structure and the second slit structure.
A semiconductor memory device, comprising:
- a source structure;
- a stacked conductive layer overlapping with the source structure;
- a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer;
- a stacked insulating layer disposed between the first select conductive layer and the stacked conductive layer and between the second select conductive layer and the stacked conductive layer;
- and
- a separation insulating structure passing through the source structure,
- wherein the separation insulating structure is disposed between the first and second select conductive layers, and
- wherein the stacked conductive layer comprises a first conductive extension that overlaps with the first select conductive layer, a second conductive extension that overlaps with the second select conductive layer, and a conductive connector that overlaps with the separation insulating structure.
A semiconductor memory device, comprising:
- a source structure;
- a stacked conductive layer overlapping with the source structure;
- a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer;
- a stacked insulating layer disposed between the first select conductive layer and the stacked conductive layer and between the second select conductive layer and the stacked conductive layer;
- a first slit structure and a second slit structure passing through the stacked conductive layer and the stacked insulating layer, and spaced apart from each other in a first direction;
- and
- a separation insulating structure disposed between the first and second slit structures,
- wherein the first and second select conductive layers are spaced apart from each other due to the first slit structure, the second slit structure, and the separation insulating structure, and
- wherein a width of the separation insulating structure is greater than widths of the first and second slit structures.
Dependencies are inferred from the claim text.