Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same

A method, comprising:

• forming a plurality of first suspended layers in a first fin and a plurality of second suspended layers in a second fin;
• forming a first interfacial layer wrapping around the first suspended layers in the first fin and a second interfacial layer wrapping around the second suspended layers in the second fin;
• forming a first high-k dielectric layer wrapping around the first interfacial layer and a second high-k dielectric layer wrapping around the second interfacial layer;
• depositing a metal layer wrapping around the first and second high-k dielectric layers;
• removing the metal layer from the first high-k dielectric layer;
• performing an annealing process, wherein during the annealing process, oxygen in an ambient environment is driven through the metal layer, the second high-k dielectric layer, and the second interfacial layer and arrives at an outer portion of the second suspended layers, such that the outer portion of the second suspended layers is converted to an oxide layer;
• and
• depositing a first gate electrode layer wrapping around the first high-k dielectric layer and a second gate electrode layer wrapping around the second high-k dielectric layer.

An integrated circuit, comprising:

• a substrate having a first region and a second region;
• a first gate-all-around (GAA) device located in the first region, the first GAA device including:
• a first channel member extending longitudinally in a first direction, and
• a first gate structure wrapping a channel region of the first channel member, the first gate structure including a first interfacial layer;
• and
• a second GAA device located in the second region, the second GAA device including:
• a second channel member extending longitudinally in the first direction, and
• a second gate structure wrapping a channel region of the second channel member, the second gate structure including a second interfacial layer, the second interfacial layer having a first portion adjacent the second channel member and a second portion over the first portion, the first portion having a weight density less than that of the second portion.