Dummy fin with reduced height and method forming same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Yao Lin, Te-Yung Liu, Chih-Han Lin
Life of this patent
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Abstract
A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.
Claims20
A method comprising:
- forming a semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions, wherein the semiconductor fin is parallel to the dummy fin;
- forming a gate stack on a first portion of the semiconductor fin and a first portion of the dummy fin;
- after the gate stack is formed, etching a second portion of the dummy fin, and simultaneously etching a second portion of the semiconductor fin to form a source/drain recess, wherein the second portion of the dummy fin is etched slower than the second portion of the semiconductor fin, and the etching is performed until an entirety of the second portion of the semiconductor fin is removed;
- and
- after the second portion of the dummy fin is etched, growing an epitaxy semiconductor region based on a second portion of the semiconductor fin, wherein the epitaxy semiconductor region is grown toward the dummy fin.
A method comprising:
- forming dielectric isolation regions extending into a semiconductor substrate, with a first semiconductor strip and a second semiconductor strip being between the dielectric isolation regions;
- replacing the second semiconductor strip with a dielectric strip;
- recessing the dielectric isolation regions, so that top portions of the first semiconductor strip and the dielectric strip protrude higher than top surfaces of the recessed dielectric isolation regions to form a semiconductor fin and a dummy fin, respectively;
- and
- after the dielectric isolation regions are recessed, recessing a first portion of the dummy fin and a first portion of the semiconductor fin in a common etching process, wherein a first top surface the first semiconductor strip is recessed to be lower than a second top surface of the first portion of the dummy fin by the common etching process.
A method comprising:
- forming a gate stack;
- forming a dielectric fin, wherein the dielectric fin comprises:
- a first portion directly underlying the gate stack;
- and
- a second portion laterally offset from the gate stack;
- forming a semiconductor fin on a side of, and parallel to, the dielectric fin, wherein the semiconductor fin comprises:
- a third portion directly underlying the gate stack;
- and
- a fourth portion laterally offset from the gate stack;
- etching the second portion of the dielectric fin, wherein when the second portion of the dielectric fin is etched, the fourth portion of the semiconductor fin is exposed to a respective etching chemical, and has a lower etching rate than the second portion of the dielectric fin;
- and
- etching the fourth portion of the semiconductor fin, wherein when the fourth portion of the semiconductor fin is etched, the second portion of the dielectric fin is exposed to a respective etching chemical, and has a lower etching rate than the fourth portion of the semiconductor fin.
Dependencies are inferred from the claim text.