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US 11,894,263 B2Granted
Local interconnect
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
Life of this patent
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Abstract
Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.
Claims20
A method, comprising:
- providing a workpiece comprising a substrate, an etch stop layer (ESL) over the substrate, a dielectric layer over the ESL, and a silicon layer over the dielectric layer;
- performing a first patterning process of the silicon layer to form a first trench and a second trench;
- performing a second patterning process of the silicon layer to form a branch opening in fluid communication with the second trench but is spaced apart from the first trench;
- forming a spacer along sidewalls of the first trench, the second trench and the branch opening;
- after the forming of the spacer, performing a third patterning process of the silicon layer to form a gate signal line trench between the first trench and the second trench;
- after the third patterning process of the silicon layer, etching the dielectric layer and the ESL using the silicon layer and the spacer as an etch mask;
- and
- depositing a metal layer over the dielectric layer and the ESL.
5 more elements
A method, comprising:
- providing a workpiece comprising a substrate, a dielectric layer over the substrate, and a silicon layer over the dielectric layer;
- forming a first trench and a second trench in the silicon layer, wherein the first trench and the second trench extend along a first direction;
- forming a branch opening in the silicon layer, wherein the branch opening is in fluid communication with the second trench;
- conformally depositing a spacer material layer over the first trench, the second trench, and the branch opening;
- etching back the spacer material layer to form a spacer along sidewalls of the first trench, the second trench and the branch opening;
- after the etching back, selectively removing the silicon layer between the first trench and the second trench without substantially removing the spacer and the silicon layer between the branch opening and the first trench;
- after the selectively removing, transferring a pattern of the silicon layer and the spacer to the dielectric layer;
- and
- depositing a metal layer over the dielectric layer.
6 more elements
A method, comprising:
- providing a workpiece comprising a substrate, a dielectric layer over the substrate, a gate contact via, a first source/drain contact via and a second source/drain contact via disposed in the dielectric layer, and a silicon layer over the dielectric layer;
- performing a first patterning process to form a first trench and a second trench in the silicon layer, wherein the first trench is disposed over the first source/drain contact via and the second trench is disposed over the second source/drain contact via;
- performing a second patterning process to form a branch opening in the silicon layer, wherein the branch opening is in fluid communication with the second trench and the branch opening is disposed over the gate contact via;
- conformally depositing a spacer material layer over the first trench, the second trench, and the branch opening;
- etching back the spacer material layer to form a spacer along sidewalls of the first trench, the second trench and the branch opening;
- after the etching back, selectively removing the silicon layer between the first trench and the second trench without substantially removing the spacer and the silicon layer between the branch opening and the first trench;
- after the selectively removing, transferring a pattern of the silicon layer and the spacer to the dielectric layer;
- and
- depositing a metal layer over the dielectric layer.
6 more elements
Dependencies are inferred from the claim text.