Duty correction device including duty correction circuit and semiconductor device including duty correction device

A semiconductor device, comprising:

• a data pad and a data strobe pad;
• a clock generation circuit configured to generate first to fourth write clock signals by dividing a write clock signal at a set ratio, the write clock signal received through the data strobe pad;
• a first alignment circuit configured to align write data in response to the first to fourth write clock signals, the write data input through the data pad, and to transmit the first to fourth write clock signals and the write data through a first clock transmission path and a first data transmission path;
• and
• first to fourth duty correction devices, each configured to receive the first to fourth write clock signals transferred through the first clock transmission path, to receive one of the first to fourth write clock signals as a reference clock signal and remaining ones of the first to fourth write clock signals as first to third divided clock signals alternatively according to phases of the first to fourth write clock signals, to detect a phase difference between the reference clock signal and the first to third divided clock signals, and to perform a duty correction operation on the reference clock signal.

A semiconductor device, comprising:

• a command pad, a clock pad, and a data strobe pad;
• a clock generation circuit configured to generate first to fourth read clock signals by dividing an external clock signal at a set ratio in response to a read command received through the command pad, the external clock signal input through the clock pad, and to transmit the first to fourth read clock signals to a first clock transmission path and the data strobe pad;
• a first alignment circuit configured to align read data in response to the first to fourth read clock signals received through the first clock transmission path, the read data output from a memory cell area, and to transmit the first to fourth read clock signals and the read data through a second clock transmission path and a first data transmission path;
• and
• first to fourth duty correction devices, each configured to receive the first to fourth read clock signals transferred through the first and second clock transmission paths, to receive one of the first to fourth read clock signals as a reference clock signal and remaining ones of the first to fourth read clock signals as first to third divided clock signals alternatively according to phases of the first to fourth read clock signals, to detect a phase difference between the reference clock signal and the first to third divided clock signals, and to perform a duty correction operation on the reference clock signal.