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AssigneeMacronix International Co., Ltd.
InventorsSu-Chueh Lo, Yi-Fan Chang
Estimating the term…
A data serializer, a latch data device using the same and a controlling method thereof are provided. The data serializer includes at least one data buffer and a de-skew buffer. The data buffer at least receives an inputting data and a controlling signal. An outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.
A data serializer, comprising:
A latch data device, comprising:
A controlling method of a data serializer, wherein the data serializer includes at least one data buffer and a de-skew buffer, and the controlling method comprises:
Dependencies are inferred from the claim text.
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Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input latches
Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor: data reordering during…
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output…
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output latches
About 15 years 5 months of term left · ends 27 Mar 2042 (estimated)
The disclosure relates in general to an electronic component, an electric device using the same and a controlling method thereof, and more particularly to a data serializer, a latch data device using the same and a controlling method thereof.
Along with the development of the semiconductor technology, several kinds of electric components are invented. For example, data buffers are widely used in the latch data device. The data buffer outputs data of “0” or “1” when an enable port is inputted a controlling signal of “1.” The data buffer disables output (or output “Hi-Z”) when the enable port is inputted the controlling signal of “0.”
In the data buffer, an outputting signal is raised to be “1” or fallen to be “0.” When the outputting signal is being raised or fallen, the content is invalid. In case of the raising time is longer than the falling time, the time period of “1” will be shorter than the time period of “0” under the controlling signal having fixed cycle time. In case of the raising time is shorter than the falling time, the time period of “1” will be longer than the time period of “0” under the controlling signal having fixed cycle time.
FIG. 1 shows a data buffer according to one embodiment.
FIG. 2 shows a logic table of the data buffer.
FIG. 3 shows a circuit diagram of the data buffer according to one embodiment.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
Referring to FIG. 1, a data buffer TB1 according to one embodiment is shown. The data buffer TB1 is, for example, a tri-state buffer TB1. The data buffer TB1 has an input port I, an enable port EN and an output port O. A controlling signal C is inputted to the enable port EN. An inputting data DA is inputted to the input port I. An outputting signal Dout is outputted from the output port O.
Please refer to FIG. 2, which shows a logic table of the data buffer TB1. The controlling signal C inputted to the enable port EN is “1” when it is at a predetermined level; the controlling signal C inputted to the enable port EN is “0”, when it is lower than the predetermined level. The output port O of the data buffer TB1 outputs the outputting signal Dout of “0” or “1” according to the inputting data DA inputted to the input port I when the controlling signal C inputted to the enable port EN is “1.” The data buffer TB1 disables output (or output “Hi-Z”) when the controlling signal C inputted to the enable port EN is “0.”