Stacked DRAM device and method of manufacture
AssigneeRambus Inc.
InventorThomas Vogelsang
Life of this patent
Estimating the term…
Abstract
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
Claims20
A memory device comprising:
- a first integrated circuit (IC) memory die including
- first memory core circuitry,
- first interface circuitry,
- a second IC memory die stacked with the first IC memory die, the second IC memory die including
- second memory core circuitry,
- second interface circuitry coupled to the second memory core circuitry and the first memory core circuitry, the second interface circuitry formed to match the first interface circuitry, the first interface circuitry formed to match the second interface circuity;
- and
- wherein the second interface circuitry of the second die is configured to transfer signals between the first memory core circuitry and a memory controller.
A memory module, comprising:
- a substrate;
- multiple memory devices mounted to the substrate, each memory device comprising
- a first integrated circuit (IC) memory die including
- first memory core circuitry,
- first interface circuitry,
- a second IC memory die stacked with the first IC memory die, the second IC memory die including
- second memory core circuitry,
- second interface circuitry coupled to the second memory core circuitry and the first memory core circuitry, the second interface circuitry formed to match the first interface circuitry, the first interface circuitry formed to match the second interface circuitry;
- and
- wherein the second interface circuitry of the second die is configured to transfer signals between the first memory core circuitry and a memory controller.
A memory, comprising:
- at least one memory module including
- a substrate;
- multiple memory devices mounted to the substrate, each memory device comprising
- a first integrated circuit (IC) memory die including
- first memory core circuitry,
- first interface circuitry,
- a second IC memory die stacked with the first IC memory die, the second IC memory die including
- second memory core circuitry,
- second interface circuitry coupled to the second memory core circuitry and the first memory core circuitry, the second interface circuitry formed to match the first interface circuitry, the first interface circuitry formed to match the second interface circuitry;
- and
- wherein the second interface circuitry of the second die is configured to transfer signals between the first memory core circuitry and a memory controller.
Dependencies are inferred from the claim text.