Memory system including a nonvolatile memory device, and an erasing method thereof

An erase method of a nonvolatile memory device, the erase method comprising:

• receiving an erase command;
• applying a first voltage, in a first erase mode based on the erase command, that causes a gate-source potential difference of a pass transistor connected to a word line to have a first value;
• detecting a leakage current on the word line when the pass transistor is off;
• identifying the word line, connected to the pass transistor that is turned off, as a fail word line;
• and
• in a second erase mode, erasing a memory block connected to the word line as a second voltage is applied that causes the gate-source potential difference to have a second value greater than the first value.

A memory system comprising:

• a nonvolatile memory device;
• and
• a memory controller configured to control the nonvolatile memory device,
• wherein the nonvolatile memory device comprises:
• a memory cell region comprising a first metal pad;
• a peripheral region comprising a second metal pad, the peripheral region being connected to the memory cell region through the first metal pad and the second metal pad;
• a memory cell array comprising a plurality of memory cells forming a plurality of strings in a direction substantially perpendicular to a substrate, the memory cell array being included in the memory cell region;
• wherein the peripheral region further comprises:
• a row decoder comprising a pass transistor configured to switch a plurality of word lines connected to the plurality of memory cells, configured to select, through the plurality of word lines, a memory block that is included in the memory cell array;
• a voltage generator included in the peripheral region and configured to generate a plurality of voltages provided to the memory cell array and the pass transistor;
• and
• a control logic included in the peripheral region and configured to decrease, based on a first erase command, a gate-source potential difference of the pass transistor to detect a leakage current of a word line in the memory block,
• wherein the memory controller is configured to count the number of erases of the memory block, issue the first erase command when the number of erases reaches a reference value, and detect the leakage current.