Selective power-on scrub of memory units
AssigneeMicron Technology, Inc.
InventorsZhenlei Shen, Tingjun Xie, Zhenming Zhou
Life of this patent
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Abstract
A system includes a memory device having groups of managed units and a processing device coupled to the memory device. The processing device, during power on of the memory device, causes a read operation to be performed at a subset of a group of managed units and determines a bit error rate related to data read from the subset of the group of managed units. The bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states. In response to the bit error rate satisfying a threshold criterion, the processing device causes a rewrite of the data stored at the group of managed units.
Claims20
A system comprising:
- a memory device comprising a plurality of groups of managed units;
- and
- a processing device operatively coupled to the memory device, the processing device to, during power on of the memory device, perform operations comprising:
- causing a read operation to be performed at a subset of a group of managed units;
- determining a bit error rate related to data read from the subset of the group of managed units, wherein the bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states;
- and
- in response to the bit error rate satisfying a threshold criterion, causing a rewrite of the data stored at the group of managed units.
A method comprising:
- detecting, by a processing device operatively coupled with a memory device, a power on of the memory device, wherein the memory device comprises a plurality of groups of managed units;
- and
- in response to detecting the power on of the memory device:
- causing, by the processing device, a read operation to be performed at a subset of a group of managed units;
- determining, by the processing device, a bit error rate related to data read from the subset of the group of managed units, wherein the bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states;
- and
- in response to the bit error rate satisfying a threshold criterion, causing, by the processing device, a rewrite of the data stored at the group of managed units.
A non-transitory computer-readable medium storing instructions, which when executed by a processing device that is operatively coupled with a memory device, performing a plurality of operations comprising:
- detecting a power on of the memory device, wherein the memory device comprises a plurality of groups of managed units;
- and
- in response to detecting the power on of the memory device and for each group of the plurality of groups of managed units:
- causing a read operation to be performed at a subset of a group of managed units;
- determining a bit error rate related to data read from the subset of the group of managed units, wherein the bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states;
- and
- in response to the bit error rate satisfying a threshold criterion, causing a rewrite of the data stored at the group of managed units.
Dependencies are inferred from the claim text.