Memory with error checking and correcting unit
AssigneeChangxin Memory Technologies, Inc.
InventorsWeibing Shang, Hongwen Li, Liang Zhang, Kangling Ji, Sungsoo Chi, Daoxun Wu, Ying Wang
Life of this patent
Estimating the term…
Abstract
A memory is provided. The memory includes banks, each bank includes a U half bank and a V half bank; a first error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of the output data of the U half banks and the V half banks.
Claims18
A memory, comprising banks, each of the banks comprising a U half bank and a V half bank;
- a first error checking and correcting unit connected with U half banks and V half banks and configured to check and correct errors of output data of the U half banks and the V half banks;
- and
- a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks;
- wherein each of the U half banks comprises an even number of block data buses, and the block data buses are sequentially numbered from zero according to natural numbers;
- wherein odd-numbered block data buses are connected with the first error checking and correcting unit, and even-numbered block data buses are connected with the second error checking and correcting unit;
- or the odd-numbered block data buses are connected with the second error checking and correcting unit, and the even-numbered block data buses are connected with the first error checking and correcting unit.
A memory, comprising banks, each of the banks comprising a U half bank and a V half bank;
- a first error checking and correcting unit connected with U half banks and V half banks and configured to check and correct errors of output data of the U half banks and the V half banks;
- and
- a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks;
- wherein each of the V half banks comprises an even number of block data buses, and the block data buses are sequentially numbered from zero according to natural numbers;
- wherein odd-numbered block data buses are connected with the first error checking and correcting unit, and even-numbered block data buses are connected with the second error checking and correcting unit;
- or the odd-numbered block data buses are connected with the second error checking and correcting unit, and the even-numbered block data buses are connected with the first error checking and correcting unit.
Dependencies are inferred from the claim text.