US 11,894,086 B2 · Method, device, and circuit for high-speed memories

Abstract

In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

Claims20

Dependent claims

A memory device, comprising:

a plurality of memory cells arranged in an array;
an input/output (I/O) interface, connected to the plurality of memory cells to output data signal from each memory cell;
and
a control circuit, comprising:
a first clock generator configured to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal, and provide the first clock signal to the plurality of memory cells;
and
a second clock generator distinct from the first clock generator, and configured to generate a third clock signal according to the input clock signal and provide the first clock generator with a design for testability (DFT) enable (DFTEN) signal;
wherein the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

5 more elements

Dependencies are inferred from the claim text.

Method, device, and circuit for high-speed memories

Life of this patent

Method, device, and circuit for high-speed memories

Life of this patent

Abstract

Claims20