Memory controller, memory system with improved threshold voltage distribution characteristics, and operation method

A memory controller of a memory device including memory cells, the memory controller comprising:

• an over-program controller configured to preprogram the memory cells in preprogramming and then erase the memory cells to set the memory cells in a first threshold voltage distribution, and to detect fast cells among the memory cells set in the first program distribution, wherein normal cells among the memory cells each have a threshold voltage equal to or greater than a first threshold voltage, and the fast cells each have a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage;
• and
• a processor configured to generate fast cell information identifying the fast cells among the memory cells and store the fast cell information in a buffer,
• wherein the over-program controller is further configured to control programming of the memory cells from the first threshold voltage distribution to a second threshold voltage distribution greater than the first threshold voltage distribution with reference to the fast cell information stored in the buffer, wherein the programming comprises:
• normal programming the normal cells to the second threshold voltage distribution by applying a sequence of incremental step pulse program (ISPP) voltage pulses to the normal cells, and
• over-programming the fast cells to the second threshold voltage distribution by applying the sequence of ISPP voltage pulses to the fast cells,
• wherein a voltage of an ISPP voltage pulses applied during over-programming is greater than a voltage of a corresponding ISPP voltage pulse applied during normal programming, and
• wherein a level of a verification voltage applied during the over-programming is greater than a level of a corresponding verification voltage applied during the normal programming.

A memory device comprising:

• a memory cell array including a first block of first memory cells and a second block of second memory cells;
• and
• control logic configured to preprogram and then erase the first memory cells such that each of the first memory cells has a first threshold voltage level, wherein fast cells are detected among the memory cells according to a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage,
• wherein the control logic is further configured to generate fast cell information associated with the fast cells and store the fast cell information in the second block, and upon receiving a program command directed to the first memory cells, over-programming the fast cells by referencing the fast cell information stored in the second memory cells, and
• wherein the control logic is further configured to compare a number of the fast cells to a reference threshold value, and
• stores the fast cell information in the second memory cells block only if the number of fast cells is greater than the reference threshold value.