Semiconductor memory device
AssigneeKioxia Corporation
InventorKoji Kato
Life of this patent
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Abstract
A semiconductor memory device according to an embodiment includes memory cell transistors, a word line, and a controller. A memory cell transistor whose threshold voltage is included in first and second states store first and second data, respectively. In a verify operation of the first data, during application of a verify high voltage of the first data to the word line, the controller is configured to determine whether or not a threshold voltage of a memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and also determine whether or not a threshold voltage of a memory cell transistor to which the second data is to be written exceeds a verify low voltage of the second data.
Claims20
A semiconductor memory device comprising:
- a plurality of memory cell transistors each capable of storing a plurality of bits of data, a threshold voltage of each of the memory cell transistors being included in one of a plurality of states, the states including a first state and a second state, the second state being higher than the first state, a memory cell transistor whose threshold voltage is included in the first state storing first data, and a memory cell transistor whose threshold voltage is included in the second state storing second data;
- a word line coupled to the memory cell transistors;
- and
- a controller configured to perform a write operation that includes a plurality of program loops each including a program operation and a verify operation,
- wherein
- a verify low voltage and a verify high voltage higher than the verify low voltage are set for each of the states, and
- in a verify operation of the first data, during application of a verify high voltage of the first data to the word line, the controller determines whether or not a threshold voltage of a memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and also determine whether or not a threshold voltage of a memory cell transistor to which the second data is to be written exceeds a verify low voltage of the second data.
A semiconductor memory device comprising:
- a plurality of memory cell transistors each storing a plurality of bits of data, each of threshold voltages of the memory cell transistors being included in one of a plurality of states, the states including a first state, and a memory cell transistor whose threshold voltage is included in the first state storing first data;
- a word line coupled to the memory cell transistors;
- a plurality of bit lines coupled to the memory cell transistors, respectively;
- and
- a plurality of sense circuits coupled to the bit lines, respectively, each of the sense circuits including a sense node, and each of the sense circuits determining a threshold voltage of a memory cell transistor, based on a voltage of the sense node;
- and
- a controller configured to perform a write operation that includes repetition of a program loop including a program operation and a verify operation,
- wherein
- a verify low voltage and a verify high voltage are set for each of the states,
- in a verify operation of the first data, the controller
- charges each of the sense nodes of the sense circuits while a first voltage intermediate between a verify low voltage of the first data and a verify high voltage of the first data is being applied to the word line, and first charges each of the sense nodes of the sense circuits and then discharges each of the sense nodes in a second time longer than the first time while the verify high voltage of the first data is being applied to the word line, and
- a sense circuit coupled to a memory cell transistor to which the first data is to be written determines whether or not a threshold voltage of the memory cell transistor to which the first data is to be written exceeds the verify low voltage of the first data while the first voltage is being applied to the word line, and determines whether or not the threshold voltage of the memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data.
Dependencies are inferred from the claim text.