US 11,894,067 B2 · Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate

Abstract

A memory apparatus and method of operation are provided. The memory apparatus includes memory cells configured to retain a threshold voltage. The memory cells are connected to one of a plurality of word lines and are arranged in strings comprising a plurality of blocks. A control means is coupled to the plurality of word lines and the strings and is configured to periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells. The control means is also configured to relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.

Claims20

Dependent claims

A memory apparatus, comprising:

memory cells configured to retain a threshold voltage and connected to one of a plurality of word lines and arranged in strings comprising a plurality of blocks;
and
a control means coupled to the plurality of word lines and the strings and configured to:
periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells, and
relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.

2 more elements

A controller in communication with a memory apparatus including memory cells configured to retain a threshold voltage and connected to one of a plurality of word lines and arranged in strings comprising a plurality of blocks, the controller configured to:

periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells;
and
instruct the memory apparatus to relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.

A method of operating a memory apparatus including memory cells configured to retain a threshold voltage and connected to one of a plurality of word lines and arranged in strings comprising a plurality of blocks, the method comprising the steps of:

periodically determining a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells;
and
relocating data of the one of the plurality of blocks and causing the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.

Dependencies are inferred from the claim text.

Facts

Application

17/551,640Filed 15 Dec 2021

Published

US 2023/0186998 A115 Jun 2023

Granted

6 Feb 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
G06F 12/00
Accessing, addressing or allocating within memory systems or architectures
G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series

Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate

Life of this patent

Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate

Life of this patent

Abstract

Claims20