Semiconductor memory device and method of operating the semiconductor memory device
AssigneeSK hynix Inc.
InventorSoo Yeol Chai
Life of this patent
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Abstract
The present technology provides a method of operating a semiconductor memory device detecting a threshold voltage distribution for memory cells included in a page selected from among a plurality of memory cells. The method of operating the semiconductor memory device includes selecting a target state in which the threshold voltage distribution is to be detected, determining a plurality of read voltages for dividing a voltage range in which a threshold voltage of the selected target state is distributed, and performing a plurality of sensing operations using the plurality of read voltages on the selected page. Masking to the target state is applied in each of the plurality of sensing operations.
Claims15
A method of operating a semiconductor memory device detecting a threshold voltage distribution for memory cells included in a page selected from among a plurality of memory cells, wherein each of the plurality of memory cells stores N bit of data, the method comprising:
- selecting a target state, in which the threshold voltage distribution is to be detected, from among an erase state and first to (2N-1)-th program states, wherein N is a natural number;
- determining a plurality of read voltages for dividing a voltage range in which a threshold voltage of the selected target state is distributed;
- and
- performing a plurality of sensing operations using the plurality of read voltages on the selected page,
- wherein masking to the target state is applied in each of the plurality of sensing operations.
A semiconductor memory device comprising:
- a plurality of memory cells connected to a selected word line;
- a plurality of page buffers configured to perform a sensing operation on each of the plurality of memory cells, wherein each of the plurality of memory cells stores N bit of data;
- and
- control logic configured to control an operation of the plurality of page buffers,
- wherein each of the plurality of page buffers comprises:
- at least one data latch connected to a sense out node and storing bit data;
- and
- a sensing latch connected to the sense out node and storing bit data indicating whether a threshold voltage of a corresponding memory cell among the plurality of memory cells is greater than a selected read voltage during a sensing operation,
- the at least one data latch stores bit data programmed to the corresponding memory cell, and
- the control logic selects a target state, in which a threshold voltage distribution is to be detected, from among an erase state and first to (2N-1)-th program states, wherein Nis a natural number, and controls each of the plurality of page buffers to apply masking of the target state to the bit data stored in the sensing latch, based on the bit data stored in the at least one data latch.
Dependencies are inferred from the claim text.