US 11,894,063 B2Granted

Semiconductor memory device

AssigneeKioxia Corporation

InventorNayuta Kariya

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Abstract

A semiconductor memory device includes first conductive layers arranged in a first direction, a second conductive layer disposed at a position overlapping with the first conductive layers viewed from the first direction, a third conductive layer disposed at a position overlapping with the first conductive layers viewed from the first direction and arranged with the second conductive layer in a second direction intersecting with the first direction, a first semiconductor column opposed to the first conductive layers and the second conductive layer, a second semiconductor column opposed to the first conductive layers and the third conductive layer, and a fourth conductive layer disposed between the second conductive layer and the third conductive layer. The fourth conductive layer has a length in the second direction smaller than a length of the second conductive layer in the second direction and a length of the third conductive layer in the second direction.

Claims20

Dependent claims

A semiconductor memory device comprising:

a substrate;
a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate;
a second conductive layer disposed at a position overlapping with the plurality of first conductive layers viewed from the first direction;
a third conductive layer disposed at a position overlapping with the plurality of first conductive layers viewed from the first direction, the third conductive layer being arranged with the second conductive layer in a second direction intersecting with the first direction;
a plurality of first semiconductor column rows arranged in the second direction;
a plurality of first electric charge accumulating layers disposed between each of a plurality of first semiconductor columns included in the plurality of first semiconductor column rows and the plurality of first conductive layers;
a plurality of second semiconductor column rows arranged in the second direction;
a plurality of second electric charge accumulating layers disposed between each of a plurality of second semiconductor columns included in the plurality of second semiconductor column rows and the plurality of first conductive layers;
a fourth conductive layer disposed between the second conductive layer and the third conductive layer, the fourth conductive layer extending in a third direction intersecting with the first direction and the second direction;
a first insulating layer disposed between the second conductive layer and the fourth conductive layer;
and
a second insulating layer disposed between the third conductive layer and the fourth conductive layer, wherein
the plurality of first semiconductor column rows each include the plurality of first semiconductor columns arranged in the third direction,
the plurality of first semiconductor columns are each opposed to the plurality of first conductive layers and the second conductive layer,
the plurality of second semiconductor column rows each include the plurality of second semiconductor columns arranged in the third direction,
the plurality of second semiconductor columns are each opposed to the plurality of first conductive layers and the third conductive layer, and
assuming that a cross-section extending in the second direction and the third direction and including one of the plurality of first conductive layers is a first cross-section, and
a distance in the second direction between center positions on the first cross-section of two first semiconductor column rows adjacent in the second direction is a first distance,
the fourth conductive layer has a length in the second direction smaller than a length of the second conductive layer in the second direction, a length of the third conductive layer in the second direction, and the first distance.

16 more elements

A semiconductor memory device comprising:

a substrate;
a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate;
a second conductive layer disposed at a position overlapping with the plurality of first conductive layers viewed from the first direction;
a third conductive layer disposed at a position overlapping with the plurality of first conductive layers viewed from the first direction, the third conductive layer being arranged with the second conductive layer in a second direction intersecting with the first direction;
a first semiconductor column extending in the first direction and opposed to the plurality of first conductive layers and the second conductive layer;
a first electric charge accumulating layer disposed between the plurality of first conductive layers and the first semiconductor column;
a second semiconductor column extending in the first direction and opposed to the plurality of first conductive layers and the third conductive layer;
a second electric charge accumulating layer disposed between the plurality of first conductive layers and the second semiconductor column;
a fourth conductive layer disposed between the second conductive layer and the third conductive layer, the fourth conductive layer extending in a third direction intersecting with the first direction and the second direction;
a first insulating layer disposed between the second conductive layer and the fourth conductive layer;
and
a second insulating layer disposed between the third conductive layer and the fourth conductive layer, wherein
the fourth conductive layer has a length in the first direction larger than a length of the second conductive layer in the first direction and a length of the third conductive layer in the first direction.

10 more elements

A semiconductor memory device comprising:

a substrate;
a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate;
a second conductive layer disposed at a position overlapping with the plurality of first conductive layers viewed from the first direction;
a third conductive layer disposed at a position overlapping with the plurality of first conductive layers viewed from the first direction, the third conductive layer being arranged with the second conductive layer in a second direction intersecting with the first direction;
a first semiconductor column extending in the first direction and opposed to the plurality of first conductive layers and the second conductive layer;
a first gate insulating film disposed between the plurality of first conductive layers and the first semiconductor column, the first gate insulating film being separated from the third conductive layer in the second direction and including a first electric charge accumulating layer;
a second semiconductor column extending in the first direction and opposed to the plurality of first conductive layers and the third conductive layer;
a second gate insulating film disposed between the plurality of first conductive layers and the second semiconductor column, the second gate insulating film being separated from the second conductive layer in the second direction and including a second electric charge accumulating layer;
a third electric charge accumulating layer disposed between the second conductive layer and the third conductive layer;
a first insulating layer disposed between the second conductive layer and the third electric charge accumulating layer;
and
a second insulating layer disposed between the third conductive layer and the third electric charge accumulating layer, wherein
a part of an outer peripheral surface of the first semiconductor column is opposed to the second conductive layer, and another part of the outer peripheral surface of the first semiconductor column is opposed to the third electric charge accumulating layer without via the second conductive layer, and
a part of an outer peripheral surface of the second semiconductor column is opposed to the third conductive layer, and another part of the outer peripheral surface of the second semiconductor column is opposed to the third electric charge accumulating layer without via the third conductive layer.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/695,060Filed 15 Mar 2022
Priority: JP 2021-13715025 Aug 2021
Published: US 2023/0069251 A12 Mar 2023
Granted: 6 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G11C 16/14
Programming or data input circuits: circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 5/06
Details of stores covered by group G11C11/00: arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits