Memory device performing program operation and method of operating the same
AssigneeSK hynix Inc.
InventorsJung Shik Jang, Dong Hun Lee, Yun Sik Choi
Life of this patent
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Abstract
A memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to perform an incremental step pulse program (ISPP) on the plurality of memory cells. The control logic is configured to control the peripheral circuit to perform the ISPP using bit line voltages set based on different bit line step voltages according to a target program state of each of the plurality of memory cells among a plurality of program states.
Claims20
A memory device comprising:
- a plurality of memory cells;
- a peripheral circuit configured to perform an incremental step pulse program (ISPP) on a selected memory cell among the plurality of memory cells to a target program state among a plurality of program states;
- and
- control logic configured to store a program setting table on bit line step voltages corresponding to the plurality of program states, respectively, and control the peripheral circuit to perform the ISPP using a bit line voltage set based on the target program state and the program setting table,
- wherein the bit line step voltages have different values from each other according to corresponding program states, respectively, in the program setting table.
A method of operating a memory device that performs an incremental step pulse program (ISPP) on a selected memory cell among a plurality of memory cells to a target program state among a plurality of program states, the method comprising:
- setting a bit line voltage based on the target program state and a program setting table on bit line step voltages corresponding to the plurality of program states, respectively;
- applying the set bit line voltage to a bit line connected to the selected memory cell;
- and
- applying a program voltage to a word line connected to the selected memory cell among the plurality of memory cells,
- wherein the bit line step voltages have different values from each other according to corresponding program states, respectively, in the program setting table.
Dependencies are inferred from the claim text.