US 11,894,054 B2 · Methods for writing ternary content addressable memory devices

Abstract

Ternary content-addressable memory (TCAM) devices are described. The TCAMs described herein are designed to perform write operations—including data writes and mask writes—in a single clock cycle. For example, data input is written in a row of the TCAM during the first portion of a clock cycle, and a mask is written in another row of the TCAM during the second portion of the clock cycle, for example immediately after or after a programmable delay from the data write. In one implementation, a first bus is used both for data write and key search operations, and a second bus is used both for mask write and search masking operations. In another implementation, a first bus is used both for data write and key search operations, a second bus is used for mask write operations, and a third bus is used for search masking operations.

Claims19

Dependent claims

An apparatus comprising:

a ternary content addressable memory (TCAM) comprising:
a first plurality of rows of memory cells configured to store a plurality of respective data inputs;
and
a second plurality of rows of memory cells configured to store a plurality of respective masks;
and
control circuitry configured to:
generate a first control signal configured to write a data input in a row of the first plurality of rows of memory cells in a first clock cycle, and
generate a second control signal configured to write a mask in a row of the second plurality of rows of memory cells in the first clock cycle, wherein the control circuitry is configured to generate the second control signal in response to an edge of the first control signal.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/716,319Filed 8 Apr 2022 · continuation in part

Priority

IN 20192104289422 Oct 2019

Published

US 2022/0230684 A121 Jul 2022

Granted

6 Feb 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 15/04
Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out…
G11C 7/1009
Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor: data masking during input/output
G11C 7/1048
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data bus control circuits, e.g. precharging,…
G11C 7/1066
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…

Family

Application17/074,789Parent of this continuation-in-part · filed 20 Oct 2020

US 2022/0230684 A1Pre-grant publication · published 21 Jul 2022

US 11,404,121 B2Parent of this continuation-in-part

US 2021/0118506 A1Published application

US 11,894,054 B2This patent

From the US filing history. Foreign family members aren’t listed.

Methods for writing ternary content addressable memory devices

Life of this patent

Methods for writing ternary content addressable memory devices

Life of this patent

Abstract

Claims19