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US 11,894,050 B2Granted
Memory with a sense amplifier isolation scheme for enhancing memory read bandwidth
AssigneeQUALCOMM Incorporated
InventorsHochul Lee, Anil Chowdary Kota, Dhvani Sheth, Chulmin Jung
Life of this patent
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Abstract
A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.
Claims15
A memory, comprising;
- a sense amplifier configured to pre-charge a pair of sense amplifier input nodes responsive to an assertion of a sense amplifier pre-charge signal;
- a self-timed memory circuit including a dummy bit line circuit configured to assert a dummy bit line output signal to trigger a de-assertion of the sense amplifier pre-charge signal;
- a first plurality of columns, each column in the first plurality of columns including a pair of bit lines;
- a first read column multiplexer configured to select a first selected column from the first plurality of columns responsive to an assertion of a first read multiplexer address signal to couple the pair of bit lines in the first selected column to the pair of sense amplifier input nodes;
- and
- a first switch coupled between a node for the first read multiplexer address signal and a power supply node, wherein the first switch is configured to open in response to the assertion of the dummy bit line output signal.
3 more elements
A memory comprising:
- a plurality of columns, each column in the plurality of columns including a pair of bit lines;
- a sense amplifier including a pair of sense amplifier input nodes;
- a read column multiplexer configured to select a selected column from the plurality of columns responsive to an assertion of a read multiplexer address signal to couple the pair of bit lines in the selected column to the pair of sense amplifier input nodes;
- a self-timed memory circuit including a dummy bit line circuit configured to prevent the assertion of the read multiplexer address signal until an assertion of a dummy bit line circuit output signal;
- and
- a first switch coupled between a node for the read multiplexer address signal and a power supply node, wherein the first switch is configured to open in response to the assertion of the dummy bit line circuit output signal.
3 more elements
Dependencies are inferred from the claim text.