Processing in memory implementing VLIW controller

A method for operating an apparatus, comprising:

• issuing a compute request associated with bit vector operations, addressed to a virtual address, from control logic on a source separate from a memory device;
• receiving the compute request at a sequencer separate from the memory device and coupled to the control logic;
• using the sequencer to convert the virtual address of the compute request to a real address corresponding to a particular column and row in an array of memory cells on the memory device;
• enabling a reduction in use of a processing resource on the memory device by reducing conversion of the virtual address to the real address by the memory device;
• receiving microcode timing instructions for a compute operation, associated with the bit vector operations at the memory device to coordinate timing of a sequence of compute sub-operations associated with the bit vector operations;
• receiving the timing instructions from the source;
• performing the sequence of compute sub-operations at the memory device using the timing instructions;
• and
• performing the compute operation using the timing instructions and using a compute component of the memory device.

A system, comprising:

• a memory device comprising compute components configured to perform bit vector operations;
• and
• a host, comprising:
• a sequencer that comprises a very large instruction word (VLIW) type controller configured to operate on compute commands associated with the bit vector operations and to:
• provide instructions for the bit vector operations to be performed by a compute component of the memory device;
• provide information to indicate a length of bit vectors and a source row address for retrieval of the bit vectors;
• and
• provide different information to indicate a length of data values and a destination row address for transfer of the data values after performance of the bit vector operations;
• control logic configured to issue the compute commands to the sequencer in response to a signal from a processing resource of the host;
• and
• timing circuitry selectably coupled to the memory device, the timing circuitry configured to control timing, associated with the bit vector operations, of performance of a compute operation using the compute components.