Apparatuses and methods for a multi-bit duty cycle monitor
OwnerDean D. Gansinventor
Life of this patent
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Abstract
Embodiments of the disclosure are drawn to apparatuses and methods for a multi-bit duty cycle monitor. A clock signal may be provided to a memory in order to synchronize one or more operations of the memory. The clock signal may have a duty cycle which is adjusted by a duty cycle adjustor of the memory. The duty cycle of the adjusted clock signal may be monitored by a multi-bit duty cycle monitor. The multi-bit duty cycle monitor may provide a multi-bit signal which indicates if the duty cycle of the adjusted clock signal is above or below a target duty cycle value (or if the duty cycle is outside tolerances around the target duty cycle). The multi-bit duty cycle monitor may provide the multi-bit signal while access operations of the memory are occurring.
Claims20
A method comprising:
- providing, with a controller, a mode register write command and a first value to a memory device, wherein the first value is configured to enable a multi-bit duty cycle monitor of the memory device;
- providing, with the controller, a mode register read command to read a multi-bit duty result from a mode register of the memory device;
- and
- based, at least in part, on the multi-bit duty result, providing, with the controller, a second mode register write command and a duty code to the memory device.
A method comprising:
- performing, with a memory device, access operations, wherein timing of the access operations is based, at least in part, on a clock signal;
- adjusting, with the memory device, a duty cycle of the clock signal based on a duty code,
- generating, with the memory device, while performing the access operations with the memory device, a signal which indicates a direction of adjustment to the duty code based at least in part on the duty cycle of the clock signal and a target duty cycle value.
An apparatus comprising:
- a memory configured to perform access operations based, at least in part, on a clock signal;
- a duty cycle adjuster configured to adjust the duty cycle of the clock signal based on a duty code;
- and
- a duty cycle monitor coupled to the adjusted clock signal and configured to provide a multi-bit signal with a state responsive to the duty cycle of the adjusted clock signal,
- wherein the state of the multi-bit signal is updated while the access operations are being performed, and wherein the duty code is increased responsive to the multi-bit signal being in a first state, and decreased responsive to the multi-bit signal being in a second state.
Dependencies are inferred from the claim text.