Power management circuit in low-power double data rate memory and management method thereof
AssigneeIntegrated Silicon Solution, Inc.
InventorShuenrun Seara Jian
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AssigneeIntegrated Silicon Solution, Inc.
InventorShuenrun Seara Jian
Estimating the term…
A power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies memory according to a reference voltage. A low dropout regulator has a first transmitting terminal and a second transmitting terminal. The low dropout regulator adjusts a voltage difference between a first voltage and a second voltage according to the reference voltage. A power network structure is electrically connected to the low dropout regulator. A first power network circuit has a first connecting point, a grid shape and a first unit network space. A second power network circuit has a second connecting point, another grid shape and a second unit network space. The second connecting point is separated from the first connecting point by a distance. The distance is smaller than or equal to one of the first unit network space and the second unit network space.
A power management circuit in a low-power double data rate memory, which is configured to manage a plurality of power supplies of the low-power double data rate memory according to a reference voltage, the power management circuit in the low-power double data rate memory comprising:
A power management circuit in a low-power double data rate memory, which is configured to manage a plurality of power supplies of the low-power double data rate memory according to a first reference voltage, a second reference voltage and a control signal, the power management circuit in the low-power double data rate memory comprising:
A management method of a power management circuit in a low-power double data rate memory, which is configured to manage a plurality of power supplies of the low-power double data rate memory according to a reference voltage, the management method of the power management circuit in the low-power double data rate memory comprising:
Dependencies are inferred from the claim text.