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US 11,894,039 B2Granted
Fft-dram
AssigneeNif/T, LLC
InventorsMammen Thomas, Robert J. Strain
Life of this patent
Estimating the term…
Abstract
A flat field transistor (FFT) based dynamic random-access memory (DRAM) (FFT-DRAM) is disclosed. The FFT-DRAM comprises an epitaxially grown source region comprising a source extension and an epitaxial source over and in contact with the source extension. The epitaxially grown source region is over a surface of a semiconductor substrate. The FFT-DRAM further comprises a trench capacitor structurally integrated into the epitaxially grown source region. The trench capacitor has a first terminal formed by the epitaxially grown source region and a second terminal being a conductive material filling one or more trenches of the trench capacitor. The second terminal is connected to a ground terminal or a fixed voltage terminal.
Claims20
A dynamic random-access memory (DRAM) cell, comprising:
- an epitaxially grown source having a doping of a second type, the epitaxially grown source over and in contact with a source region of a surface of a semiconductor substrate, the semiconductor substrate having a doping of a first type opposite to the second type, forming a junction at an interface between the source region of the surface of the semiconductor substrate and the epitaxially grown source;
- an epitaxially grown drain having a doping of the second type, the epitaxially grown drain over and in contact with a drain region of the surface of the semiconductor substrate, the semiconductor substrate having a doping of the first type opposite to the second type, forming a junction at an interface between the drain region of the surface of the semiconductor substrate and the epitaxially grown drain;
- a gate structure on the surface of the substrate, separating the source region and the drain region of the surface of the semiconductor substrate, the gate structure having a gate dielectric separating a conductive gate electrode from the surface of the semiconductor substrate;
- a pass gate comprising the conductive gate electrode enabled to create a conductive channel in the semiconductor substrate under the gate dielectric, the conductive channel electrically connecting the epitaxially grown source over the source region and the epitaxially grown drain over the drain region when a gate voltage in excess of a threshold voltage of a pass transistor is applied to the conductive gate electrode;
- a capacitor structurally integrated into the epitaxially grown source, the capacitor having a first terminal connected to the epitaxially grown source and a second terminal connected to a ground terminal or a fixed voltage terminal;
- and
- a capacitor dielectric separating the first and second terminals of the capacitor;
- wherein
- when the pass transistor is turned on, the first terminal of the capacitor is electrically connected to a bit line connected to the epitaxially grown drain;
- and
- when the pass transistor is turned off, the first terminal of the capacitor is isolated from the bit line connected to the epitaxially grown drain.
8 more elements
A dynamic random-access memory (DRAM) device integratable with a silicon integrated circuit (IC), the DRAM device comprising:
- an epitaxial source having a doping of a second dopant type, the epitaxial source being over a first portion of a surface of a substrate, the substrate having a doping of a first dopant type, creating a junction at an interface between the epitaxial source and the substrate, the epitaxial source being connected structurally to a first terminal of a capacitor, the capacitor having a first conductive layer structurally connected to the epitaxial source forming the first terminal of the capacitor, a second terminal of the capacitor being formed by a second conductive layer separated from the first conductive layer by a capacitor dielectric layer, the second conductive layer being connected to a ground or a fixed voltage source via a metal interconnect;
- an epitaxial drain having a doping of the second dopant type, the epitaxial drain being over a second portion of the surface of the substrate, the substrate having a doping of the first dopant type, creating a junction at an interface between the epitaxial drain and the substrate, the epitaxial drain being connected to a bit line;
- and
- a pass gate being over the surface of the substrate between the epitaxial source and the epitaxial drain, the pass gate being configured to form a channel in the substrate connecting the epitaxial source and the epitaxial drain when a gate voltage in excess of a threshold voltage of a pass transistor of the DRAM device is applied to a gate electrode, the gate electrode connecting to a word line enabled to turn the pass transistor on or off by the application of the gate voltage.
1 more element
A dynamic random-access memory (DRAM) device, comprising:
- a gate having a conductive gate electrode positioned over a gate dielectric;
- a first portion of an epitaxial drain and a first portion of an epitaxial source on a surface of a substrate, the first portion of the epitaxial drain and the first portion of the epitaxial source formed over and in contact with respective source and drain regions of the surface of the substrate, the epitaxial drain and epitaxial source being isolated from the conductive gate electrode by a first dielectric, the epitaxial drain and epitaxial source forming respective junctions at their interfaces with the respective drain and source regions of the surface of the substrate;
- and
- a second portion of the epitaxial source over the first portion of the epitaxial source and a second portion of the epitaxial drain over the first portion of the epitaxial drain, the respective second portions of the epitaxial source and the epitaxial drain being isolated from the conductive gate electrode by a second dielectric;
- the epitaxial source, the epitaxial drain and the gate together forming a pass transistor enabled to connect the epitaxial source to the epitaxial drain when a voltage value in excess of a threshold value is applied to the conductive gate electrode;
- the source region having one or more charge storage capacitors, each charge storage capacitor having one of its terminals connected to the epitaxial source to store charge responsive to data being stored, the charge storage capacitor having first and second conductive electrodes separated by a capacitor dielectric, the first conductive electrode having its terminal coupled to the epitaxial source, the second conductive electrode being isolated from the epitaxial source and the first conductive electrode by the capacitor dielectric, and the second conductive electrode being connected to a ground terminal or a fixed voltage terminal;
- wherein
- a channel of the pass transistor forms a path connecting the first terminal of the charge storage capacitor to a bit line connected to the epitaxial drain when a gate voltage in excess of a threshold voltage is applied to the conductive gate electrode to turn on the pass transistor;
- and
- the channel of the pass transistor is turned off, when the gate voltage is removed from the conductive gate electrode to isolate the terminal of the first conductive electrode of the charge storage capacitor from the bit line.
7 more elements
Dependencies are inferred from the claim text.