Display device configured to output gate signals to at least two gate lines at a time having output timings different from each other, and control method therefor

A display device comprising:

• a panel driving unit comprising panel driving circuitry;
• a display panel including a plurality of pixels connected with a plurality of gate lines and a plurality of data lines through a plurality of switching elements comprising switching circuitry;
• and
• a processor configured to:
• control the panel driving unit to output gate signals through the plurality of gate lines including a first gate line, a second gate line and a third gate line, and control the panel driving unit to apply, through the plurality of data lines, a data voltage to the plurality of pixels connected with the plurality of switching elements to which the gate signals were output,
• wherein the processor is configured to:
• in a first mode, control the panel driving unit to sequentially output gate signals to the plurality of gate lines one gate line at a time to process image data in a first driving frequency, and
• in a second mode, control the panel driving unit to output gate signals to the plurality of gate lines at least two gate lines at a time to process image data in a second driving frequency higher than the first driving frequency,
• wherein, in the second mode,
• respective ones of the gate signals output to the plurality of gate lines at least two gate lines at a time have output timings different from each other, and
• controlling the panel driving unit to output the gate signals to the plurality of gate lines at least two gate lines at a time includes:
• controlling the panel driving unit to output a first gate signal to a plurality of switching elements connected to the first gate line through the first gate line at a first timing,
• controlling the panel driving unit to output a second gate signal to a plurality of switching elements connected to the second gate line through the second gate line at a second timing, and
• controlling the panel driving unit to output a third gate signal to a plurality of switching elements connected to the third gate line through the third gate line at a third timing,
• wherein a plurality of pixels connected with the second gate line are charged by a third value based on a first value by which a plurality of pixels connected to the first gate line are charged and a second value by which a plurality of pixels connected to the third gate line are charged, and
• wherein the third value is different from the first value and the second value.