Pixel circuit, display panel and display apparatus

A display panel, comprising a pixel circuit, wherein the pixel circuit comprises:

• a first resetting switching transistor, a first data writing switching transistor, a storage capacitor, a first compensation capacitor, a second compensation capacitor, and a driving transistor;
• wherein the first resetting switching transistor comprises a first switching sub-transistor and a second switching sub-transistor connected in series, and the first data writing switching transistor comprises a third switching sub-transistor and a fourth switching sub-transistor connected in series;
• wherein,
• gates of the first switching sub-transistor and the second switching sub-transistor are both electrically connected to a first scanning signal line, a first electrode of the first switching sub-transistor is electrically connected to a first node, a first electrode of the second switching sub-transistor is electrically connected to a resetting signal line, and a second electrode of the first switching sub-transistor and a second electrode of the second switching sub-transistor are both electrically connected to a fourth node;
• a gate of the driving transistor is electrically connected to the first node, and a first electrode of the driving transistor is electrically connected to a first power supply line;
• gates of the third switching sub-transistor and the fourth switching sub-transistor are both electrically connected to a second scanning signal line, a first electrode of the third switching sub-transistor is electrically connected to the first node, and a first electrode of the fourth switching sub-transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the third switching sub-transistor and a second electrode of the fourth switching sub-transistor are both electrically connected to a third node;
• the storage capacitor is electrically connected to the first power supply line and the first node respectively;
• a first end of the first compensation capacitor is electrically connected to the first power supply line, and a second end of the first compensation capacitor is electrically connected to the third node;
• a first end of the second compensation capacitor is electrically connected to the resetting signal line, and a second end of the second compensation capacitor is electrically connected to the fourth node;
• the first compensation capacitor and the second compensation capacitor are used to enable a voltage Vn1′ of the first node to be smaller than a voltage Vn3 of the third node and larger than a voltage Vn4′ of the fourth node in a light-emitting stage;
• wherein the pixel circuit further comprises an active layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer;
• the first end of the first compensation capacitor is the first power supply line located in the source-drain metal layer, the second end of the first compensation capacitor is arranged in a same layer as a conductive region of the active layer, the first gate metal layer, or the second gate metal layer.

A display apparatus, comprising a display panel, wherein the display panel comprises a pixel circuit, and the pixel circuit comprises:

• a first resetting switching transistor, a first data writing switching transistor, a storage capacitor, a first compensation capacitor, a second compensation capacitor, and a driving transistor;
• wherein the first resetting switching transistor comprises a first switching sub-transistor and a second switching sub-transistor connected in series, and the first data writing switching transistor comprises a third switching sub-transistor and a fourth switching sub-transistor connected in series;
• wherein,
• gates of the first switching sub-transistor and the second switching sub-transistor are both electrically connected to a first scanning signal line, a first electrode of the first switching sub-transistor is electrically connected to a first node, a first electrode of the second switching sub-transistor is electrically connected to a resetting signal line, and a second electrode of the first switching sub-transistor and a second electrode of the second switching sub-transistor are both electrically connected to a fourth node;
• a gate of the driving transistor is electrically connected to the first node, and a first electrode of the driving transistor is electrically connected to a first power supply line;
• gates of the third switching sub-transistor and the fourth switching sub-transistor are both electrically connected to a second scanning signal line, a first electrode of the third switching sub-transistor is electrically connected to the first node, and a first electrode of the fourth switching sub-transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the third switching sub-transistor and a second electrode of the fourth switching sub-transistor are both electrically connected to a third node;
• the storage capacitor is electrically connected to the first power supply line and the first node respectively;
• a first end of the first compensation capacitor is electrically connected to the first power supply line, and a second end of the first compensation capacitor is electrically connected to the third node;
• a first end of the second compensation capacitor is electrically connected to the resetting signal line, and a second end of the second compensation capacitor is electrically connected to the fourth node;
• the first compensation capacitor and the second compensation capacitor are used to enable a voltage Vn1′ of the first node to be smaller than a voltage Vn3′ of the third node and larger than a voltage Vn4′ of the fourth node in a light-emitting stage;
• wherein the pixel circuit further comprises an active layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer;
• the first end of the first compensation capacitor is the first power supply line located in the source-drain metal layer, the second end of the first compensation capacitor is arranged in a same layer as a conductive region of the active layer, the first gate metal-layer, or the second gate metal layer.